PCB Recess Portions for Plating Thickness Control
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Solution Overview
Problem
The increasing integration density of circuits in printed circuit boards leads to reduced pitch between circuits and bumps, making assembly more difficult, particularly in server CPUs with many layers, resulting in challenges in controlling chip area thickness variation (CTV) and plating thickness distribution.
Innovation Solution
A printed circuit board design with an insulating layer, recess portions, and circuit layers where the ground and power patterns cover recesses, reducing plating thickness deviations by varying via density and using these recesses to adjust thickness and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers of the printed circuit board is increased to improve integration density, then the circuit functionality is enhanced, but the accumulated distribution of the plating thickness cannot be corrected afterward, leading to increased chip area thickness variation
Solution Approach 1:
The patent applies preliminary action by forming recess portions in the insulating layer before depositing the circuit patterns. This allows the plating thickness to be pre-adjusted in areas with high via density, compensating for the accumulated thickness variation that would otherwise occur in multi-layer boards. The recess portions are created in advance to ensure uniform final plating thickness across different regions.
Solution Approach 2:
The patent implements local quality by creating recess portions only in specific regions where via density is high and plating thickness accumulation is problematic. Different regions of the insulating layer have different properties - some areas have recess portions while others remain flat, allowing localized correction of plating thickness distribution without affecting the entire board structure.
2Quantity of substance
If the pitch between circuit and bump is reduced to improve integration density, then more circuits can be packed, but the difficulty of assembling silicon die and substrate increases
Solution Approach 1:
The recess portions are formed in advance before the circuit patterns are deposited, allowing the board structure to be pre-prepared for fine-pitch assembly. This preliminary structural adjustment ensures that the plating thickness is optimized in critical areas, thereby improving assembly yield even when the pitch between circuit and bump is reduced.
3Reliability
If the via density is increased in certain areas to improve interlayer connection, then the electrical connectivity is enhanced, but the plating thickness deviation between via-concentrated areas and other areas increases
Solution Approach 1:
The patent applies local quality by creating recess portions specifically in regions with high via density. This allows the via-concentrated areas to have pre-compensated plating thickness, ensuring that the enhanced electrical connectivity does not come at the cost of excessive plating thickness deviation. The recess portions are localized to match the via density distribution pattern.
4Reliability
If the plating thickness is increased to improve signal quality, then the electrical performance is enhanced, but the chip area thickness variation increases
Solution Approach 1:
The recess portions are formed in advance to pre-compensate for areas where plating thickness would otherwise be excessively thick due to high via density. This allows the final plating thickness to be optimized for signal quality while maintaining uniform chip area thickness variation, as the recess portions provide a foundation that levels out the thickness accumulation.
Data Source
AI summary
A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.