PCB Reference Plane Design for Crosstalk Noise Reduction
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Solution Overview
Problem
Printed circuit boards (PCBs) face increased electromagnetic interference (EMI) due to high-speed operations and high device density, leading to signal delay, distortion, and crosstalk noise, which are exacerbated by the coupling between adjacent signal traces, and current return paths in conventional designs, necessitating a solution to improve signal quality.
Innovation Solution
The design incorporates additional conductive layers on the substrate's surface and bottom, with strategically placed via holes and openings filled with conductive materials to create reference planes that electrically connect to ground or power potentials, reducing crosstalk noise and EMI by minimizing the coupling coefficient between signal nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional conductive layers and via holes are added to create reference planes, then crosstalk noise and EMI are reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
The reference plane is segmented into multiple conductive layers (second conductive layer on outermost insulating layer, third conductive layer on substrate bottom surface) connected by via holes, allowing the EMI shielding function to be distributed across different PCB surfaces rather than requiring a single complex layer
Solution Approach 2:
The reference plane extends from a two-dimensional trace pattern into the third dimension by adding conductive layers on both the top and bottom surfaces of the PCB, connected through via holes, creating a three-dimensional EMI shielding structure that blocks electromagnetic interference from multiple directions
2Ease of manufacture
If conventional current return paths are used in high-speed signal traces, then manufacturing is simpler, but electromagnetic interference and signal quality degrade
Solution Approach 1:
A reference plane acts as an intermediary structure between signal traces and the ground, providing a dedicated low-impedance return path for high-speed signals. The reference plane (comprising second and third conductive layers connected by via holes) mediates the electromagnetic field distribution, preventing EMI while maintaining manufacturing simplicity
Solution Approach 2:
The reference plane creates an equipotential surface at a fixed voltage level (typically ground or power voltage) beneath or adjacent to signal traces. This equipotential structure provides a stable reference potential for high-speed signals, reducing voltage fluctuations and EMI while maintaining a simple two-layer PCB manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses crosstalk noise and mitigates EMI, improving signal quality and reducing manufacturing costs compared to multi-layered PCBs, while maintaining high-speed data transmission capabilities.
Implementation Method 1
The reference plane is configured to provide electromagnetic shielding to reduce crosstalk noise between the signal nets
Implementation Method 2
strategically placed via holes and openings filled with conductive materials to create reference planes that electrically connect to ground or power potentials
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A printed circuit board (PCB) is disclosed. The PCB (200) includes a substrate (202) have a top surface (202a) and a bottom surface (202b). A first conductive layer (203) is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net (203a) and a second signal net (203b). An outermost insulating layer (204) is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening (209) to expose a portion of the second signal net. And, a second conductive layer (207) is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential. The thickness of outermost insulating layer (204) is less than 1 mm.