PCB Fine Pattern Formation via Seed Layer Embedding and Over-etching
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Solution Overview
Problem
Existing printed circuit board manufacturing methods, such as subtractive and semi-additive processes, face challenges in forming fine patterns due to the negative relationship between illuminance and surface contact, leading to alignment issues, high costs, and low productivity, as well as the risk of electrical shorts and ion migration.
Innovation Solution
A method involving the formation of a circuit pattern on an insulating layer with a seed layer, embedding the pattern using a press method, and over-etching to ensure the circuit layer is lower than the surface, reducing ion migration and improving pattern reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the illuminance of the insulating layer surface is increased to improve contact with photosensitive material, then the contact between insulating layer and photosensitive material is improved, but fine Cu remains in rough insulating material during plating and delamination, causing electrical short and preventing fine pattern formation
Solution Approach 1:
A flatting layer is formed on the insulating layer surface before forming the circuit pattern. This preliminary action creates a smooth surface that enables good contact with photosensitive material while preventing Cu residue during plating, thus resolving the contradiction between contact quality and fine pattern formation
Solution Approach 2:
The flatting layer acts as an intermediary between the insulating layer and the circuit pattern. It provides a smooth surface for photosensitive material contact while being removed later, thus mediating between the need for good contact and the need for clean fine pattern formation without electrical short
2Manufacturing precision
If conventional embedding method is used to form circuit pattern on carrier substrate, then circuit can be embedded in insulating layer, but alignment problems occur and circuit pattern may not be embedded at desired position
Solution Approach 1:
The circuit pattern formation process is merged with the insulating layer structure by forming the pattern directly on the insulating layer (with flatting layer) rather than on a separate carrier substrate. This integration eliminates alignment problems between carrier and insulating layer, simplifying the device structure while maintaining embedding capability
3Productivity
If conventional manufacturing methods are used, then productivity is maintained, but fine pattern formation is limited due to surface illuminance issues
Solution Approach 1:
The flatting layer is formed as a preliminary step before circuit pattern formation. This additional layer enables fine pattern formation by providing a smooth surface, while the overall process remains compatible with conventional manufacturing workflows, maintaining productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of fine patterns without alignment issues, enhances reliability, and reduces the risk of inferior circuits due to ion migration, while maintaining cost-effectiveness and productivity.
Implementation Method 1
embedding the circuit pattern into the insulating layer by a press method
Implementation Method 2
over-etching to ensure the circuit layer is lower than the surface
Data Source
AI summary
The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.