PCB Seed Layer Stack for Thin-Via Adhesion and Coverage

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Solution Overview

Problem

The challenge in chiplet technology is to achieve high adhesion and excellent coverage in via holes of printed circuit boards with miniaturized seed layers, particularly in semi-additive processes, to accommodate smaller line widths and separation distances.

Innovation Solution

A printed circuit board design incorporating a first seed metal layer formed with a titanium sputtering layer on an organic insulating material, followed by a second seed metal layer using electroless plating, ensuring both high adhesion and coverage in via holes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of substance

If a thin seed layer is used to minimize flash etching in semi-additive process, then the amount of flash etching is reduced, but the adhesion to insulating material and coverage in via hole deteriorate

Engineering Contradiction:
Improveamount of flash etchingVSAvoidadhesion and coverage property
Core Design Contradiction:
Loss of substanceVSReliability

Solution Approach 1:

The seed metal layer is divided into multiple layers with different materials and functions. The first seed metal layer (Ti, W, or Mo) provides adhesion to the organic insulating material, while the second seed metal layer (Cu or Al) provides coverage in via holes and serves as the reflective layer. This segmentation allows each layer to be optimized for its specific function, resolving the contradiction between minimizing flash etching and maintaining adhesion/coverage properties.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention uses composite material structure combining different metals (Ti, W, Mo, Cu, or Al) in a layered configuration. Each material is selected for its specific properties: Ti/W/Mo for adhesion to organic materials, and Cu/Al for via hole coverage and reflectivity. This composite approach enables the seed layer to simultaneously achieve minimal flash etching consumption and excellent adhesion/coverage properties.

Inventive Principle:
Principle #40Composite materials

2Length of moving object

If the seed layer is made thinner to accommodate miniaturization, then the line width and separation distance are reduced, but the adhesion to organic insulating material and coverage in via hole worsen

Engineering Contradiction:
Improveline widthVSAvoidadhesion and coverage property
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The seed layer is segmented into two functional layers: the first layer (Ti, W, or Mo) specialized for adhesion to organic insulating materials, and the second layer (Cu or Al) specialized for via hole coverage. This segmentation enables the overall seed layer to be thin for miniaturization while each sub-layer maintains sufficient thickness for its specific function, resolving the contradiction between line width reduction and adhesion/coverage maintenance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the seed layer structure have different material compositions optimized for local requirements. The first seed metal layer composition is optimized for adhesion to organic materials, while the second seed metal layer is optimized for via hole coverage and reflectivity. This local quality differentiation allows the structure to maintain high reliability in both adhesion and coverage despite overall miniaturization.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides enhanced adhesion and coverage properties, supporting the miniaturization requirements of chiplet technology by securing stable connections in via holes.

Implementation Method 1

a first seed metal layer including a first sputtering layer having titanium (Ti)

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 2

a second seed metal layer disposed on the first seed metal layer and extending onto a wall surface of the via hole and the exposed upper surface of the first metal layer; and a second metal layer disposed on the second seed metal layer and filling at least a portion of the via hole, wherein the first seed metal layer includes a first sputtering layer having titanium (Ti), and the second seed metal layer includes an electroless plating layer

Methodology Applied
Scientific EffectElectroless plating: Electroplating

Data Source

PatentUS12526919B2Printed circuit board
Publication Date: 2026.01.13 SAMSUNG ELECTRO MECHANICS CO LTD
  • US12526919B2 patent drawing
  • US12526919B2 patent drawing
  • US12526919B2 patent drawing

AI summary

A printed circuit board includes: a first metal layer; an organic insulating layer covering at least a portion of the first metal layer and having a via hole exposing at least a portion of an upper surface of the first metal layer; a first seed metal layer disposed on an upper surface of the organic insulating layer; a second seed metal layer disposed on the first seed metal layer and extending onto a wall surface of the via hole and the exposed upper surface of the first metal layer; and a second metal layer disposed on the second seed metal layer and filling at least a portion of the via hole, wherein the first seed metal layer includes a first sputtering layer including titanium (Ti), and the second seed metal layer includes an electroless plating layer.