PCB Signal Integrity via Non-Adjacent Reference Planes
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Solution Overview
Problem
Existing printed circuit boards (PCBs) in semiconductor memory systems face challenges in maintaining high signal line impedance and signal integrity due to the structural layout, which affects the performance of memory modules.
Innovation Solution
The PCB design includes a specific layer configuration where signal lines are connected through vias to reference planes not directly adjacent to them, and power/ground planes are strategically positioned with slits beneath signal lines to enhance signal integrity by increasing impedance and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reference planes are disposed in layers directly adjacent to signal lines, then signal integrity is improved through closer electrical reference, but signal line impedance decreases due to stronger coupling
Solution Approach 1:
The patent moves the reference plane from the adjacent layer (traditional configuration) to a non-adjacent layer, changing the spatial dimension of the reference plane's location. This dimensional shift allows the signal line to maintain better impedance control while still achieving signal integrity through the repositioned reference plane configuration.
Solution Approach 2:
The patent implements partial planes in specific layers rather than complete reference planes in all adjacent layers. By selectively placing reference plane portions only where needed for signal integrity while avoiding areas that would adversely affect impedance, the design achieves local optimization of both parameters.
2Reliability
If power/ground planes are placed in all layers, then electrical reference and signal integrity are improved, but interference and noise increase
Solution Approach 1:
The patent extracts or removes power/ground planes from certain layers where they would cause interference, while retaining them in specific layers where they provide beneficial electrical reference. This selective extraction eliminates harmful interference while preserving the necessary signal integrity functions.
Solution Approach 2:
Instead of uniformly placing power/ground planes in all layers, the patent applies local quality by configuring planes only in specific layers and specific regions. This localized approach ensures that planes provide electrical reference where needed while avoiding creation of interference in other areas.
3Adaptability or versatility
If signal lines are connected through multiple layers, then connection flexibility and routing options increase, but signal transmission distance increases causing degradation
Solution Approach 1:
The patent utilizes multi-layer configuration with strategic via placement to manage signal transmission. By carefully selecting which layers to connect and where to place vias, the design achieves routing flexibility while controlling the effective transmission distance through optimized vertical and horizontal signal paths.
Solution Approach 2:
The patent uses vias as intermediary elements to connect signal lines between layers. These via structures serve as mediators that enable layer-to-layer connectivity while minimizing signal degradation, allowing flexible routing across multiple layers without excessive transmission distance in any single continuous path.
Data Source
AI summary
A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved.