PCB Thick-Wall Vias via Segmented Plating
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Solution Overview
Problem
Existing methods for manufacturing printed circuit boards with high current carrying capacity conductive vias are suboptimal, leading to increased thickness of outer conductive layers, incompatibility with miniaturization technology, and irregular surface morphology, which hinders the use of fine pitch components and reduces power density.
Innovation Solution
A multi-step plating process is used to form conductive vias with different sidewall thicknesses, maintaining thin outer conductive layers and via pads while achieving thick via sidewalls, allowing for improved power density and compatibility with fine pitch components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single plating process is used to form conductive vias with thick sidewalls, then the current carrying capacity is improved, but the outer conductive layers become too thick for compatibility with miniaturization technology
Solution Approach 1:
The plating process is divided into multiple sequential steps: first forming via holes, then selectively plating via sidewalls in a first plating step, and finally forming outer conductive layers in subsequent steps. This segmentation allows independent control of via wall thickness and outer layer thickness, resolving the contradiction between achieving thick via walls for current carrying capacity and maintaining thin outer layers for miniaturization compatibility.
Solution Approach 2:
Different regions of the conductive structure are given different thicknesses: the via sidewalls are plated to achieve thick walls (e.g., 5-10 mils) for high current carrying capacity, while the outer conductive layers are maintained at thin thicknesses (e.g., 1-3 mils) for compatibility with fine pitch components. This local differentiation of quality resolves the contradiction between local current carrying needs and global miniaturization requirements.
2Reliability
If known methods are used to form conductive vias with different sidewall thicknesses, then current carrying capacity is improved, but thin-wall vias have non-planar surface morphology requiring additional processing
Solution Approach 1:
The via holes are formed with predetermined dimensions and the selective plating is performed in a controlled sequence before final outer layer formation. By preliminarily establishing the via structure with appropriate sidewall thicknesses through selective plating, the process avoids the need for subsequent planarization steps, as the surface morphology is already suitable for the next processing stage.
3Power
If thick via sidewalls are formed to increase power density, then current carrying capacity is improved, but the manufacturing process becomes less compatible with fine pitch components
Solution Approach 1:
The manufacturing process is segmented into distinct stages: via hole formation, selective via sidewall plating, and outer conductive layer formation. This segmentation allows the via structures to be optimized for power density with thick sidewalls while the outer layers are independently controlled to maintain thin profiles compatible with fine pitch components, thus resolving the adaptability contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in printed circuit boards with reduced electrical resistance, lower resistive heating, and enhanced board space utilization, enabling the use of fine pitch components and increasing power and component density.
Implementation Method 1
selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively
Data Source
AI summary
In at least one illustrative embodiment, a printed circuit board may comprise at least one insulating layer, first and second conductive layers separated from one another by the at least one insulating layer, and a conductive via extending through the at least one insulating layer and electrically coupling the first and second conductive layers. The conductive via may include an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches) and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches).