PCB Via Hole Formation Doubles Interlayer Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing PCB connector design, which relies on through-hole crimping, limits the space between wafers, making it difficult to increase connector density and channel rate simultaneously due to tight spacing and poor control over backdrilling depth and stub length.
Innovation Solution
A PCB processing method involving lamination of daughter boards, drilling, and electroplating to form blind and through holes, with backdrilling from the side of subsequent layers to create metallized blind holes and through holes, allowing for increased spacing between wafers without reducing connector density, and enabling effective connector crimping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If through hole crimping is used for connector mounting, then connector mounting is achieved, but the space between wafers is limited and wiring space is constrained
Solution Approach 1:
The patent divides the connector mounting hole into two separate processing stages: first forming a blind hole through lamination and partial drilling, then completing the through hole after connector placement. This segmentation allows the upper PCB layer to have sufficient thickness for connector crimping while maintaining reduced overall through-hole depth, thereby increasing wafer spacing.
Solution Approach 2:
The patent performs preliminary lamination and blind hole formation before final connector mounting. By pre-forming the blind hole to a controlled depth and then completing the through hole after connector placement, the method achieves better depth control and reduced stub length while maintaining ease of connector mounting.
2Manufacturing precision
If deeper backdrilling is performed on through holes, then connector mounting depth is achieved, but depth tolerance increases and stub control deteriorates
Solution Approach 1:
The backdrilling process is segmented into two stages: first backdrilling the via hole to a controlled depth before lamination, then completing the through hole backdrilling after lamination. This segmentation reduces the total backdrilling depth required in each stage, improving stub control and reducing depth tolerance issues.
Solution Approach 2:
The patent performs preliminary backdrilling of via holes to a controlled depth before final lamination, establishing a foundation that limits the subsequent backdrilling depth needed. This preliminary action significantly reduces the final backdrilling depth requirement, improving manufacturing precision for stub control.
3Quantity of substance
If connector density is increased, then communication capacity is improved, but the space for layout between wafers is reduced
Solution Approach 1:
The patent changes the dimensional approach by using blind holes with controlled depth instead of traditional deep through holes. This dimensional change in hole structure allows reduced wafer thickness requirements, thereby increasing the space between wafers while maintaining high connector density through optimized vertical space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method doubles the space between wafers while maintaining connector density, reducing stub length and enhancing wiring space efficiency by forming blind holes through multiple laminations and strategic backdrilling, optimizing connector placement and wiring patterns.
Implementation Method 1
respectively carrying out lamination processing on a plurality of PCB daughter boards constituting a PCB
Implementation Method 2
drilling and electroplating a top-most PCB daughter board of the PCB to form at least one via hole
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present invention discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB according to PCB design requirements, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present invention, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.