PCB Via Placement for Noise Reduction

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Solution Overview

Problem

Existing printed circuit board (PCB) design methods, such as single-ended analysis, often result in overly conservative spacing and excessive ground vias between differential pairs, leading to wasted space and inefficiencies in trace and component placement due to excessive noise interference.

Innovation Solution

The technique involves positioning ground vias symmetrically about the perpendicular bisector between trace vias to balance the electromagnetic noise effect, allowing for closer spacing and reduced ground via count, thereby reducing noise interference and enabling higher routing density and bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If ground vias are positioned asymmetrically or excessively between differential pairs, then noise interference is reduced, but space is wasted and routing density decreases

Engineering Contradiction:
Improvenoise interferenceVSAvoidrouting density
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent applies asymmetry by positioning ground vias asymmetrically relative to the differential pair structure. Specifically, ground vias are placed closer to one trace of the differential pair than the other, creating an asymmetric configuration that strategically directs electromagnetic shielding where most needed, thereby reducing noise interference while minimizing space consumption and maintaining high routing density.

Inventive Principle:
Principle #4Asymmetry

2Object-affected harmful factors

If conservative spacing is used between differential pairs, then noise interference is reduced, but trace and component placement efficiency decreases

Engineering Contradiction:
Improvenoise interferenceVSAvoidplacement efficiency
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent applies local quality by implementing non-uniform spacing between differential pairs. Instead of applying uniform conservative spacing across all pairs, the spacing is locally optimized based on specific noise considerations, component locations, and signal integrity requirements for each differential pair, thereby reducing noise interference where critical while maintaining placement efficiency elsewhere.

Inventive Principle:
Principle #3Local quality

3Object-affected harmful factors

If excessive ground vias are placed between differential pairs, then noise interference is reduced, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvenoise interferenceVSAvoidvia count
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies partial action by implementing a selective ground via placement strategy. Rather than placing ground vias uniformly or excessively between all differential pairs, ground vias are placed only where specifically needed based on noise analysis, signal integrity requirements, and electromagnetic compatibility considerations. This partial placement approach reduces noise interference in critical areas while minimizing the total via count, thereby reducing device complexity and manufacturing cost.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes noise interference, allowing for tighter trace pair spacing and increased cross-sectional bandwidth, while maintaining signal integrity and meeting noise threshold requirements.

Implementation Method 1

The flow of electrical signals through a trace or a via on a PCB may create electromagnetic waves that may affect the flow of electrical signals through other traces or vias in the PCB. The electromagnetic waves may be referred to as noise, interference, or crosstalk.

Methodology Applied
Scientific EffectElectromagnetic noise: Electromagnetic Induction

Data Source

PatentUS10383213B1Placement of vias in printed circuit board circuits
Publication Date: 2019.08.13 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10383213B1 patent drawing
  • US10383213B1 patent drawing
  • US10383213B1 patent drawing

AI summary

In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.