PCB Via Partitioning via Plating Resist
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Solution Overview
Problem
Existing printed circuit board (PCB) technologies face challenges in minimizing signal degradation due to stub effects caused by excessive conductive material in plated via structures, which lead to increased bit error rates and costs associated with backdrilling, a process that is inaccurate, time-consuming, and costly.
Innovation Solution
The use of plating resist to selectively control the formation of conductive material within via structures, creating electrically isolated segments that only allow necessary conductive material for signal transmission, thereby reducing or eliminating stubs and improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plating resist is used to selectively control conductive material formation, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Plating resist is applied to the via structure before the plating process to predefine the regions where conductive material should be deposited. This preliminary action ensures that the partitioning is established before plating occurs, achieving high precision without requiring complex real-time control during the plating process.
Solution Approach 2:
The plating resist acts as an intermediary material between the via structure and the conductive plating material. It mediates the deposition process by allowing conductive material to form only in desired regions while blocking other areas, thereby simplifying the overall control mechanism while maintaining high precision.
2Manufacturing precision
If sequential processing is used to manufacture vias with short stubs, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent combines multiple functions into a single plating process step. By applying plating resist before plating, the process simultaneously achieves via formation, stub length control, and electrical isolation in one operation, eliminating the need for sequential processing steps and thereby improving productivity while maintaining precision.
Solution Approach 2:
The plating resist is applied in advance to define the final via structure geometry before plating occurs. This preliminary definition allows the plating process to directly create the desired short-stub via structure without requiring subsequent processing steps, thus improving manufacturing efficiency.
3Ease of manufacture
If plated via structures extend completely through the PCB, then ease of manufacture is improved, but harmful factors increase
Solution Approach 1:
The plating resist is used to extract or remove the harmful stub portions from the via structure by preventing conductive material deposition in those regions. This selective exclusion eliminates the stub effect while maintaining the simplicity of the through-hole plating process, as the resist pattern defines the desired via geometry during a single plating operation.
Solution Approach 2:
The plating resist applies different properties to different regions of the via structure. Areas covered by plating resist receive no conductive material (creating electrical isolation), while exposed areas receive full plating. This local differentiation eliminates stubs in specific regions while maintaining conductive paths where needed, resolving the stub effect without complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal integrity by reducing signal degradation, increases wiring density, and reduces production costs and time by allowing simultaneous partitioning of via structures, making the process more efficient and accurate compared to traditional backdrilling methods.
Implementation Method 1
a interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist to form a partitioned plated through hole
Data Source
Figure 1~2
Figure 3
Figure 4~8
AI summary
A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.