Printed Wiring Board Via Conductors Smooth Inner Wall Surface
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Solution Overview
Problem
Existing printed wiring boards face issues with stress concentration and crack formation in via conductors due to uneven inner wall surfaces of via holes, leading to reliability concerns and signal propagation delays.
Innovation Solution
A printed wiring board design featuring a base substrate with a cavity, an electronic component, a resin insulating layer containing inorganic particles with smooth inner wall surfaces, and via conductors formed from a seed layer and electrolytic plating layer, which suppresses stress concentration and crack formation by ensuring a smooth inner wall surface for the seed layer and improved electrolytic plating layer filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via holes with uneven inner wall surfaces are used, then manufacturing is simpler, but stress concentration and crack formation occur in via conductors
Solution Approach 1:
The patent changes the physical parameter of the via hole inner wall surface from rough/uneven to smooth by introducing inorganic particles with smooth surfaces (such as glass beads) into the resin insulating layer. This parameter change eliminates stress concentration and crack formation in via conductors while maintaining manufacturing feasibility through established processes like injection molding or compression molding with particle reinforcement.
Solution Approach 2:
The patent creates a composite resin insulating layer by combining resin material with inorganic particles (such as glass beads, silica, or alumina). This composite structure provides both the mechanical support needed for via hole formation and the smooth inner wall surface required for reliable via conductor attachment, resolving the contradiction between manufacturing simplicity and via conductor reliability.
2Reliability
If via conductors are formed in via holes with rough inner wall surfaces, then manufacturing process is simpler, but signal propagation delays occur
Solution Approach 1:
The patent modifies the surface roughness parameter of the via hole inner wall by incorporating inorganic particles with smooth surfaces into the resin insulating layer. This parameter change reduces signal propagation delays by eliminating irregularities that cause electromagnetic interference, while the overall device complexity remains manageable through standard composite material processing techniques.
3Reliability
If inorganic particles are added to resin insulating layer, then via conductor reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary action by pre-mixing inorganic particles with the resin material before forming the insulating layer. This preliminary mixing ensures uniform particle distribution throughout the resin, eliminating the need for complex post-processing to control particle placement and reducing manufacturing precision requirements during the via hole formation stage.
Solution Approach 2:
The patent uses composite material technology to create a homogeneous mixture of resin and inorganic particles. This composite approach ensures consistent particle distribution and smooth inner wall surfaces throughout the insulating layer, maintaining manufacturing precision while achieving via conductor crack resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The smooth inner wall surfaces enhance the reliability of the printed wiring board by reducing crack occurrence in via conductors and minimizing signal propagation delays, resulting in a high-quality board with consistent signal transmission.
Implementation Method 1
via conductors formed in the resin insulating layer and each including a seed layer and an electrolytic plating layer formed on the seed layer
Data Source
AI summary
A printed wiring board includes a base substrate, an electronic component accommodated in a cavity formed in the substrate, a resin insulating layer formed on the substrate such that the insulating layer is covering the electronic component, a conductor layer formed on the insulating layer, and via conductors formed in the insulating layer and each including a seed layer and an electrolytic plating layer formed on the seed layer such that the via conductors are connecting the conductor layer and electrodes of the electronic component. The insulating layer includes resin and inorganic particles and has via holes in which the via conductors is formed respectively such the inorganic particles include first inorganic particles having smooth surfaces and second inorganic particles embedded in the insulating layer and that an inner wall surface of each of the via holes includes the resin and the smooth surfaces of the first inorganic particles.