Printed Circuit Board Via Structure for Dense, Reliable Routing
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Solution Overview
Problem
The increasing number of circuits and vias in substrates for signal transmission in high-performance electronic devices necessitates a design with higher integration density, reduced substrate area, and fewer layers, while existing methods face limitations in reducing the scale of core insulating layers.
Innovation Solution
The printed circuit board design features through-holes with wider upper and lower sides than the via pads, incorporating grooves on the via surfaces, and wider pads in build-up layers to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of circuits and vias is increased to achieve high performance, then signal transmission capability is improved, but substrate area and number of layers increase
Solution Approach 1:
The patent transitions from planar circuit layout to three-dimensional vertical stacking, enabling multiple signal transmission paths through different layers and via structures. This dimensional change allows increased signal transmission capability without proportional increase in substrate area, as circuits are arranged vertically rather than only horizontally.
Solution Approach 2:
The patent implements nested via structures where smaller vias are positioned within or adjacent to larger vias, creating multiple signal paths within a compact footprint. This nesting approach allows multiple circuits to share the same vertical column space, increasing functional density without expanding substrate area.
2Productivity
If the substrate area is reduced to improve integration density, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates via offset structures and enlarged via openings that provide manufacturing tolerances and alignment buffers. These design features compensate for potential misalignment during the manufacturing process, allowing high integration density to be achieved without requiring extremely tight manufacturing precision.
Solution Approach 2:
The patent employs different via structures at different locations - with wider openings and offset positions at critical alignment points, and standard structures elsewhere. This localized optimization provides enhanced manufacturing tolerance where needed while maintaining high integration density overall, rather than requiring uniform high precision across the entire substrate.
3Area of stationary object
If the core insulating layer is scaled down to reduce substrate area, then area efficiency is improved, but via reliability deteriorates
Solution Approach 1:
The patent uses composite insulating layer structures combining different materials with complementary properties. The core insulating layer is designed with specific material compositions that maintain via adhesion and structural integrity even at reduced thickness, preventing via reliability deterioration while enabling area reduction.
Solution Approach 2:
The patent incorporates via offset structures and enlarged via openings that provide manufacturing tolerances and alignment buffers. These design features compensate for potential misalignment during the manufacturing process, allowing high integration density to be achieved without requiring extremely tight manufacturing precision.
Data Source
AI summary
A printed circuit board includes a first insulating layer; a through-hole penetrating a region between an upper surface and a lower surface of the first insulating layer; a first via disposed in at least a portion of the through-hole; a first pad connected to an upper side of the first via; and a second pad connected to a lower side of the first via. A width of the through-hole on an uppermost side is greater than a width of the first pad. At least a portion of an upper surface of the first via exposed from the first pad is recessed below the upper surface of the first insulating layer.