PCB Via Array Terminal Placement for Signal Integrity
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Solution Overview
Problem
In dense and high-speed printed circuit board (PCB) designs, there is a challenge in placing small electrical components close to active components within limited physical space to optimize signal quality and reduce noise, especially in larger and more complex PCB designs.
Innovation Solution
The solution involves creating a PCB with an array of vias forming repetitive rows and columns, and positioning electrical terminals adjacent to these vias without contacting them, allowing for the placement of electrical components within the array to optimize signal routing and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If small electrical components are used to fit within limited space, then area utilization is improved, but reliability deteriorates due to increased risk of short circuits and manufacturing defects
Solution Approach 1:
The patent applies local quality by creating distinct zones within the via array: electrical terminals are positioned in specific locations where they can closely approach vias without contact, while maintaining adequate spacing in other areas. This localized optimization allows components to be placed as close as possible to active components (improving area utilization) while ensuring minimum clearance requirements are met (maintaining reliability).
Solution Approach 2:
The patent employs preliminary action by pre-positioning electrical terminals in optimized locations within the via array before component placement. The terminals are strategically located to maximize proximity to active components while pre-establishing safe clearance zones, thereby resolving the space-reliability conflict before the actual component mounting process occurs.
2Area of stationary object
If electrical terminals are positioned close to vias, then area utilization is improved, but manufacturing precision requirements increase due to tighter tolerances
Solution Approach 1:
The patent uses preliminary action by pre-defining the positions of electrical terminals relative to the via array in the PCB design stage. The terminals are positioned to achieve maximum area utilization while pre-establishing adequate clearance margins that account for manufacturing tolerances, thereby reducing the actual precision requirements during production.
Solution Approach 2:
The patent applies beforehand cushioning by incorporating clearance zones between electrical terminals and vias that exceed the minimum required spacing. These additional clearance margins act as a buffer against manufacturing variations, allowing terminals to be positioned closer to vias (improving area utilization) while maintaining robust tolerance margins (reducing manufacturing precision requirements).
Data Source
AI summary
In one implementation, a PCB having an array of vias and electrical terminals disposed on the side of the PCB opposite the side configured to receive a grid array package are disclosed herein. The array of vias have pads and forms a pattern of repetitive rows and columns. A substantially consistent intervia distance is defined along an intervia axis between each adjacent via in each of the rows and columns. A pair of electrical terminals are positioned adjacent one another along an electrical terminal axis between at least two of the vias and the electrical terminal axis intersects the intervia axis. In another implementation, a group of four adjacent vias form a substantially rectangular shape having one of four vias positioned at each of four corners of the rectangular shape. One electrical terminal is positioned within the four vias without contacting any of the four vias.