Printed Wiring Board Warping Control via Layered Thermal Expansion
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Solution Overview
Problem
Printed wiring boards face challenges in minimizing warping during the reflow process, which can lead to short circuits and connection failures due to differences in thermal expansion coefficients between various layers, affecting the reliability and yield of IC chip mounting.
Innovation Solution
The design incorporates a core substrate with through-hole conductors and buildup layers featuring interlayer resin insulation layers with controlled thermal expansion coefficients, where the uppermost layer has a higher thermal expansion coefficient than the lowermost layer, using varying amounts of inorganic particles and resin to manage stress and prevent warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the thermal expansion coefficients of interlayer resin insulation layers are made uniform, then the manufacturing process is simplified, but warping occurs during the reflow process due to stress accumulation
Solution Approach 1:
The patent applies local quality by making the thermal expansion coefficients of interlayer resin insulation layers non-uniform. Specifically, the thermal expansion coefficient is intentionally varied between different interlayer resin insulation layers to compensate for stress differences caused by thickness variations, thereby preventing warping while maintaining manufacturing feasibility
Solution Approach 2:
The patent changes the thermal expansion coefficient parameter of the interlayer resin insulation layers. By adjusting this parameter to be different across layers based on their thickness, the patent optimizes stress distribution during temperature changes in the reflow process, preventing warping without requiring uniform material properties
2Stability of the object's composition
If through holes are formed to become narrower from upper surface toward lower surface, then warping is reduced, but manufacturing complexity increases due to precise laser control requirements
Solution Approach 1:
The patent changes the geometric parameters of through holes by forming them with varying cross-sectional areas along their length. The holes are designed to become narrower from the upper surface toward the lower surface of the core substrate, which compensates for thermal stress and reduces warping during the reflow process
3Reliability
If the distance between C4 pads and IC chip electrodes is maintained, then connection reliability is improved, but warping causes short circuits between adjacent pads
Solution Approach 1:
The patent changes the thermal expansion coefficient parameters of interlayer resin insulation layers to create a non-uniform stress distribution that compensates for warping. This allows the distance between C4 pads and IC chip electrodes to be maintained at optimal values for connection reliability, while the controlled warping prevents short circuits between adjacent pads
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warping, enhances connection reliability, and improves the mounting yield of IC chips by maintaining the distance between C4 pads and IC chip electrodes, preventing short circuits and ensuring stable interlayer resin insulation layers.
Implementation Method 1
The interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set higher than a thermal expansion coefficient of the interlayer resin insulation layer of the second buildup layer
Data Source
AI summary
A printed wiring board includes a core substrate including an insulative substrate, a first conductive layer formed on first surface of the insulative substrate, and a second conductive layer formed on second surface of the insulative substrate, a first buildup laminated on first surface of the core and including an interlayer insulation layer, a conductive layer formed on the insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer, and a second buildup laminated on second surface of the core and including an interlayer insulation layer, a conductive layer formed on the interlayer insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer. The insulation layer of the first buildup has thermal expansion coefficient set higher than thermal expansion coefficient of the insulation layer of the second buildup.