PCB Wiring Layout to Prevent Conductive Pattern Peeling
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Solution Overview
Problem
The existing method of manufacturing printed circuit boards can result in peeling of the electrically conductive pattern from the base film during the etching process, particularly due to the removal of the electroless plating layer and seed layer.
Innovation Solution
The printed circuit board design includes a base film with an electrically conductive pattern where the first and second wiring portions are 1.1 to 4.0 times the width of the third wiring portions, and a seed layer, electroless plating layer, and electroplating layer made of copper, with a void density at the interface between the electroless and electroplating layers of 5.5 μm²/μm or less, to enhance adhesion and prevent peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the electroless plating layer and seed layer are removed by etching to form the final wiring pattern, then the wiring portions are defined with precise spacing, but the electrically conductive pattern may peel off from the base film
Solution Approach 1:
The patent applies different width ratios to different wiring portions: end wiring portions (first and second) have widths of 1.1 to 4.0 times the average width of intermediate wiring portions (third). This local variation in geometry provides enhanced adhesion at critical end regions where peeling is most likely to occur during etching, while maintaining standard dimensions for intermediate portions.
Solution Approach 2:
The patent preemptively addresses the peeling risk by designing wider end wiring portions before the etching process begins. This geometric cushioning at the ends provides a buffer that prevents peeling propagation during the subsequent removal of electroless plating and seed layers, ensuring pattern integrity throughout manufacturing.
2Length of moving object
If the wiring portions are made thinner to reduce overall pattern thickness, then the board becomes more compact, but the adhesion strength decreases and peeling becomes more likely
Solution Approach 1:
The patent strategically thickens only the end wiring portions (first and second) to 1.1 to 4.0 times the width of intermediate portions, providing localized adhesion reinforcement where peeling stress is highest, while allowing intermediate portions to maintain thinner, more compact dimensions for overall size reduction.
Solution Approach 2:
The patent creates a composite wiring structure where end portions and intermediate portions have different dimensions. This composite approach combines the adhesion benefits of thicker end regions with the compactness advantages of thinner intermediate regions, achieving both goals simultaneously.
3Strength
If the wiring portions are made thicker to improve adhesion and prevent peeling, then the pattern becomes more robust, but the overall board size and complexity increase
Solution Approach 1:
The patent applies the thickness increase strategy selectively only to end wiring portions (first and second) rather than uniformly across all wiring portions. This localized approach provides the necessary adhesion strength at critical peeling-prone locations while avoiding unnecessary complexity and material usage in intermediate portions.
Solution Approach 2:
The patent modifies the width parameter of end wiring portions to be 1.1 to 4.0 times that of intermediate portions. This parameter change provides a simple, quantifiable design rule that balances adhesion requirements with manufacturing simplicity, avoiding overly complex pattern designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses the peeling of the electrically conductive pattern from the base film, even when the pattern is thin or thick, and reduces side etching, maintaining adhesion despite voids at the interface.
Implementation Method 1
the electroless plating layer is formed by performing electroless plating on the seed layer
Implementation Method 2
by performing electroplating, the electroplating layers on the electroless plating layer exposed from the opening portions of the resist pattern are formed
Data Source
AI summary
A printed circuit board includes a base film having a main surface, and an electrically conductive pattern disposed on the main surface. A normal line of the main surface is along a first direction. The electrically conductive pattern includes a plurality of wiring portions disposed side by side along a second direction to be spaced apart from each other, the second direction being orthogonal to the first direction. The plurality of wiring portions include a first wiring portion and a second wiring portion that are each present at a corresponding one of both ends in the second direction and a plurality of third wiring portions that are present between the first wiring portion and the second wiring portion in the second direction.