PCH-CPLD-BIOS Architecture for Server Signal Path Conflict Resolution
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Solution Overview
Problem
Server computers without a baseboard management controller (BMC) experience read/write conflicts due to the lack of signal path management, which complicates maintenance and data access.
Innovation Solution
A computer architecture comprising a platform controller hub (PCH), field replaceable unit (FRU), memory, complex programmable logic device (CPLD), and BIOS chip, where the CPLD generates a reset signal to switch between manufacturer and normal modes, making the memory inaccessible to the PCH in manufacturer mode and the FRU accessible, thus preventing conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If a BMC is embedded to manage signal paths, then maintenance convenience is improved, but device complexity increases
Solution Approach 1:
The patent extracts the BMC component entirely from the system, replacing it with a simplified architecture using PCH, CPLD, and BIOS chip combinations. The BMC's signal path management functions are distributed to these existing components, eliminating the need for a dedicated BMC while maintaining management capabilities.
Solution Approach 2:
The PCH is designed to perform multiple functions including signal path management, memory control, and FRU management. The BIOS chip provides universal control across different operational modes (normal mode and manufacturer mode), replacing the specialized BMC functions with multi-functional existing components.
2Device complexity
If a BMC is removed to reduce device complexity, then device complexity decreases, but read/write conflicts occur
Solution Approach 1:
The system dynamically switches between normal mode and manufacturer mode based on operational requirements. The BIOS chip detects the operational mode and selectively enables or disables access paths to memory and FRU, preventing read/write conflicts by ensuring only one component can access the signal path at a time.
Solution Approach 2:
The system performs preliminary mode detection and configuration before executing read or write operations. The BIOS chip determines whether the system is in normal mode or manufacturer mode beforehand, and pre-configures the appropriate access paths, preventing conflicts before they occur.
3Productivity
If memory is always accessible to PCH for normal operation, then normal mode performance is improved, but manufacturer mode maintenance becomes difficult
Solution Approach 1:
The accessibility of memory to PCH is dynamically controlled based on operational mode. In normal mode, memory is fully accessible for high-performance operations. In manufacturer mode, the BIOS chip blocks PCH access to memory while enabling FRU access, allowing maintenance personnel to safely modify FRU components without risking memory corruption or system instability.
Data Source
AI summary
A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.