Data Resetting TRIZ Cases
- Remote Power Cycling via Network Packet and Physical Line
- Integrated On-Chip Power-On Reset Circuit for Functional Safety
A fully integrated power-on reset circuit with redundant three-stage voltage detection monitors internal rails without external components.
- PCH-CPLD-BIOS Architecture for Server Signal Path Conflict Resolution
A PCH, CPLD, and BIOS chip architecture dynamically switches signal paths to prevent read-write conflicts between memory and field replaceable units.
- I2C Bus Stability Recovery via Clock Cycling and Stop Bits
A logic module restores unstable I2C bus synchronization by cycling the clock line and transmitting stop bits to realign communication.
- Subsystem Error Handler for Targeted Communication Device Reset
Segmenting error handling into independent subsystems allows targeted resets that minimize downtime while maintaining overall device functionality.
- Watchdog Circuit Backup Power Isolation
A watchdog circuit isolates primary ground from backup power using a controlled ground switch.
- PCIe Controller Lane Reversal for EDSFF Board Height
Lane reversal in a PCIe controller enables rear surface mounting, resolving EDSFF height restrictions while maintaining signal integrity.
- Persistent Virtual Disk Reservations via Distributed iSCSI Targets
A coordinator module manages persistent reservations for virtual disks across multiple controller virtual machines.
- Relay-Based Memory Reset Circuit for Automated CMOS Clearing
A relay-based hardware circuit positioned between the battery and system settings memory interrupts power to clear data contents.
- Hypervisor Selective Function Reset in Virtualized ASICs
A hypervisor manages switching between physical and virtual functions to reset a malfunctioning unit without affecting others.
- I/O Device Safe Mode Boot Recovery
A hardware device autonomously transitions to a safe mode configuration during startup.
- VoIP Adapter Secure Configuration File Exchange
A VoIP adapter downloads encrypted configuration files using a default key and updates to a new key for secure network service.
- Remote Monitoring of Disconnected Electronic Apparatus
Low order monitoring agents acquire apparatus management information from disconnected electronic devices.
- Serial Bootstrap Mechanism for SoC Pin Reduction
Shift registers serialize bootstrap data via one pin, eliminating multiplexing conflicts and preserving signal integrity.
- FIFO Memory Credit Score Mechanism for Data Transmission Efficiency
A FIFO memory system calculates write and read credit scores to determine available space for intelligent data handling.
- Signal Control Unit Masks Reset Signals for Power Saving
A signal control unit masks operation stop signals to peripheral devices during power state transitions.
- Reset Generation Block Clock Stop Synchronization
A reset generation block stops the clock signal for defined cycles to synchronize flip-flop resets without complex buffering.
- Integrated Package and VM Configuration Management
Unified management server tracks software packages and virtual machine configurations to resolve version inconsistencies across development stages.
- Virtual Factory Reset Preserving User Settings
A virtual boot mechanism preserves user settings during a clean system restart.
- Reset Synchronization Circuit for Multi-Socket SoC Global Counter Distribution
A reset synchronization circuit generates a global counter reset signal distributed to multiple system-on-chips.
- Instrumentation Point Selection for Application Performance Monitoring
A method selects instrumentation points by running the application in development mode and monitoring component invocation patterns.
- Baseboard Management Controller Boot Resiliency via Logic Device Monitoring
Logic device monitors BMC boot status and issues power-on reset signals to recover from lockups, ensuring reliable platform security.
- Semiconductor Time Management Unit for RTOS Power Mode Transitions
Segmented counters mask interrupts and track elapsed time during low power mode, correcting internal time deviation upon returning to normal operation.
- Trusted Computing Group Platform Registers Secure Boot
A resettable binding platform configuration register decouples authorization from integrity measurements in secure boot systems.
- Multi-Controller Status Disposal for System Recovery
A status disposal unit clears stale execution results between controllers to maintain consistent operation across different operating systems.
- BMC UBM Protocol Implementation via Software Stack
A BMC executes Universal Backplane Management commands through an internal software stack.
- Embedded Device Boot Randomization Against Fault Injection
Randomizer component generates timeout signals after random intervals to prevent fault injection attacks during embedded device boot.
- Browser Plugin Disabling via Virtual Capability Reporting
A browser application detects plugin installation status and reports virtual capability data to web servers.
- Centralized Event Tags for SMP Synchronization
Centralized event tags manage synchronization across hierarchical chip interfaces.
- Electronic Device Interface Boot Identification
Dual interface architecture acquires device information during booting to resolve identification delays and enable faster function extension.
- Nondestructive Testing Apparatus Automatic Function Assignment
A nondestructive testing apparatus automatically assigns unlocked functions to input portions via a control section.