Reset Generation Block Clock Stop Synchronization
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Solution Overview
Problem
Conventional systems face challenges in resetting large numbers of flip-flops within a single clock cycle due to differing signal arrival times, leading to complexity and potential errors, especially in System on Chip (SOC) architectures, which require numerous buffers increasing costs and chip area usage.
Innovation Solution
A method involving a reset generation block that stops the clock for a defined number of cycles (N) and restarts it after another number of cycles (M), allowing for extended reset recovery times without the need for extensive buffering, enabling synchronized reset operations across multiple flip-flop arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reset arrangements are used with multiple flip-flops, then reset operations can be performed, but signal arrival times differ causing complexity and potential errors
Solution Approach 1:
The patent applies preliminary action by stopping the clock signal before performing reset operations. This preemptive measure allows all flip-flops to be reset simultaneously without worrying about signal propagation delays, as the clock is halted during the reset period. The clock is restarted after reset completion, ensuring synchronized operation across all flip-flops without requiring complex buffering arrangements.
2Manufacturing precision
If buffers are added to synchronize reset signals, then reset timing can be improved, but chip area and cost increase
Solution Approach 1:
The invention uses preliminary action by halting the clock signal before reset operations. This eliminates the need for buffers to synchronize reset signals, as the clock stoppage naturally synchronizes all flip-flop resets regardless of their position in the reset tree. This approach achieves precise reset timing without consuming additional chip area for buffer components.
Solution Approach 2:
The patent extracts and removes the need for buffer components from the reset arrangement. By using clock stoppage instead of signal buffering, the design eliminates numerous buffer units that would otherwise be required to synchronize reset signals across different flip-flop locations, thereby reducing chip area while maintaining reset timing precision.
3Productivity
If reset operations are performed in a single clock cycle, then productivity is maintained, but timing paths become complex requiring numerous buffers
Solution Approach 1:
The patent applies preliminary action by stopping the clock before reset operations. This allows reset operations to be performed without timing path constraints, as the clock halt provides a natural synchronization point. After reset completion, the clock is restarted, ensuring all flip-flops are synchronized. This approach maintains productivity by providing deterministic reset behavior without requiring complex timing paths or numerous buffers.
4Reliability
If clock is stopped for reset operations, then reset synchronization is achieved, but operational time is lost
Solution Approach 1:
The patent uses preliminary action by stopping the clock only for the minimal duration required to complete reset operations. The clock halt duration is optimized to be just long enough to ensure all flip-flops are reset and stabilized, then the clock is immediately restarted. This minimizes operational time loss while ensuring reliable reset synchronization across all flip-flops.
Data Source
AI summary
A method and apparatus for performing operations of an electrical device, whereby the apparatus performs operations during operation of a clock producing a clock signal, asserts a reset of components performing operations for the electrical device, stops the clock through a reset generation block for a number N cycles and performs the reset of operations during the stopping of the clock through the reset generation block for the number N cycles.