Serial Bootstrap Mechanism for SoC Pin Reduction
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Solution Overview
Problem
Existing system on chip (SoC) devices face signal integrity and operational issues due to multiplexing of bootstrap pins with functional pins, leading to potential incorrect bootstrap values and interference with external devices.
Innovation Solution
Implementing a serial mechanism within the SoC that uses shift registers to receive and serially sample bootstrap data, reducing the need for multiple bootstrap pins and avoiding signal integrity issues by utilizing a single physical pin for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bootstrap pins are used to transfer bootstrap data, then the data transfer capacity is sufficient, but signal integrity issues and interference occur due to multiplexing with functional pins
Solution Approach 1:
The patent combines multiple parallel bootstrap pins into a single serial communication channel. The shift register serially outputs multiple bootstrap data bits through one pin, eliminating the need for multiple pins and avoiding multiplexing conflicts with functional pins, thereby resolving signal integrity issues.
Solution Approach 2:
The shift register acts as an intermediary device between the parallel bootstrap data sources and the single serial communication pin. It converts parallel data into serial form, enabling data transfer through a single pin without direct connection conflicts, thus maintaining signal integrity.
2Area of stationary object
If bootstrap pins are multiplexed with functional pins to save I/O pad real estate, then device area is reduced, but signal integrity and timing issues occur
Solution Approach 1:
The patent merges the function of multiple bootstrap pins into a single pin by using serial communication with a shift register. This consolidation eliminates the need for multiplexing bootstrap and functional pins, saving I/O pad real estate while avoiding signal integrity and timing issues associated with multiplexing.
3Reliability
If a single pin is used for serial bootstrap data transfer, then signal integrity is maintained and pin count is reduced, but data transfer requires more time
Solution Approach 1:
The shift register transfers bootstrap data bits in periodic sequential pulses through the single pin. While serial transfer takes more time than parallel, the periodic clocked operation ensures reliable timing and signal integrity, and the reduced pin count eliminates multiplexing conflicts that would otherwise cause errors and retransmissions.
Data Source
AI summary
Approaches in accordance with various embodiments can be used to provide bootstrap data for a computing device, such as a system on chip (SoC). In particular, various embodiments can use one or more shift registers to receive bits of a sequence of bootstrap data in parallel. Individual bits of this bootstrap data sequence can then be provided to the SoC, from the shift register(s), serially and using a single input. Such an approach prevents the need for multiple bootstrap pins on the SoC, as well as the need to multiplex those pins for use with other external devices.