Semiconductor Time Management Unit for RTOS Power Mode Transitions

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Solution Overview

Problem

In semiconductor devices using RTOS, transitioning to a low power mode to reduce power consumption results in internal time deviation due to stopped time updates, leading to operational faults and synchronization issues upon returning to normal mode.

Innovation Solution

The semiconductor device employs a time management unit with a first counter for periodic counting and interrupt signal transmission, a second counter for counting during low power mode, and circuits for masking and unmasking interrupt signals, allowing for accurate time management and correction upon mode transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the semiconductor device transitions to a low power mode to reduce power consumption, then power consumption is reduced, but internal time deviation occurs due to stopped time updates

Engineering Contradiction:
Improvepower consumptionVSAvoidtime control reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The time management unit is segmented into two independent counters: a first counter that operates continuously to maintain accurate time tracking, and a second counter that operates only during low power mode to track time specifically in that state. This segmentation allows the system to reduce power consumption while maintaining time control reliability through the continuously operating first counter.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first counter acts as an intermediary that continues to track time accurately even when the main processor is in low power mode. The time management unit uses this intermediary counter to prevent internal time deviation, allowing the processor to benefit from reduced power consumption without sacrificing time control reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If the processor stops updating internal time in low power mode, then power consumption is reduced, but synchronization issues occur upon returning to normal mode

Engineering Contradiction:
Improvepower consumptionVSAvoidtime synchronization
Core Design Contradiction:
Use of energy by moving objectVSStability of the object's composition

Solution Approach 1:

The first counter continues to count time in advance during low power mode, preparing accurate time data before the processor returns to normal mode. The time management unit reads the current count value from the first counter and appropriately handles the time, ensuring that time synchronization is maintained without requiring the processor to actively update internal time during power-saving states.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If the first counter continues periodic counting during mode transitions, then time tracking accuracy is maintained, but interrupt signal coordination becomes complex

Engineering Contradiction:
Improvetime tracking accuracyVSAvoidinterrupt signal coordination
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The time tracking function is extracted from the main processor and assigned to the dedicated first counter, which operates independently and continuously. This extraction simplifies the overall system by separating the time tracking responsibility from the processor's main functions, even though the first counter continues periodic counting during mode transitions. The time management unit handles the coordination of interrupt signals based on the first counter's count values.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10049060B2Semiconductor device and control method of the same
Publication Date: 2018.08.14 KK TOSHIBA
  • US10049060B2 patent drawing
  • US10049060B2 patent drawing
  • US10049060B2 patent drawing

AI summary

A semiconductor device includes a processor for running a real-time operating system (RTOS). The RTOS causes the processor to update internal time during a first mode and to stop updating in a second mode. A first counter periodically transmits an interrupt signal to the processor that is coordinated with a periodic counting sequence. A second counter counts while the semiconductor device is in the second mode. A first circuit reads a first count value from the first counter at a starting time of a transition from the first to the second mode, masks the interrupt signal, and causes the second counter to start counting. A second circuit unmasks the interrupt signal from the first counter after a starting time of a transition from the second to the first mode and reads a second count value from the second counter.