Reset Synchronization Circuit for Multi-Socket SoC Global Counter Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for distributing a global counter value across a multi-socket system-on-chip (SoC) complex are complex and costly, leading to reduced global counter clock frequency and performance, as they require complex synchronization methods and relaxed timing requirements to account for variations between SoCs.
Innovation Solution
A reset synchronization circuit generates a global counter reset signal that is distributed simultaneously to multiple SoCs, ensuring a common base time value across all sockets, while allowing for individual adjustment of intra-socket timing and maintaining a faster global counter clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronous distribution methods are used to distribute global counter value across multi-socket SoC complex, then synchronization between SoCs is achieved, but device complexity and cost increase
Solution Approach 1:
The patent segments the distribution system into two independent parts: (1) a simplified global reset signal distribution path that resets all SoCs simultaneously, and (2) individual local counter increment operations within each SoC. This segmentation eliminates the need for complex synchronized distribution of counter values across all sockets, reducing distribution complexity while maintaining synchronization through the common reset mechanism.
2Reliability
If conventional synchronous distribution methods are used to distribute global counter value, then synchronization is achieved, but the global counter clock frequency must be reduced
Solution Approach 1:
The patent applies preliminary action by distributing the reset signal to all SoCs before the global counter clock begins incrementing. This ensures all SoCs are synchronized to the same base time value beforehand, allowing the global counter clock to run at its maximum frequency without requiring complex real-time synchronization during counter operations.
3Device complexity
If relaxed timing requirements are applied to account for SoC variations, then distribution complexity is reduced, but performance decreases
Solution Approach 1:
The patent introduces a dedicated reset synchronization circuit as an intermediary component that generates and distributes the global reset signal to all SoCs. This intermediary ensures precise simultaneous resetting of all SoCs despite variations in their individual timing characteristics, maintaining high performance while simplifying the overall distribution architecture compared to synchronizing every counter operation.
Data Source
AI summary
Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.