PCIe Controller Lane Reversal for EDSFF Board Height
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Solution Overview
Problem
The challenge in the development of solid state drives (SSDs) is to achieve miniaturization and higher speed while adhering to stricter height restrictions and improving heat dissipation, particularly with the Enterprise and Data Center SSD Form Factor (EDSFF) standard, where traditional mounting methods restrict board layout flexibility and increase signal line crossings.
Innovation Solution
The implementation of a controller with a physical layer interface circuit and PCIe MAC layer circuits that utilize Lane Reversal to rearrange lane orders, allowing for flexible board layouts and reduced signal line crossings, along with a switching circuit to manage Sideband signals, enabling efficient signal processing and heat dissipation by mounting the controller on the rear surface of the board, thus avoiding height restrictions and enhancing cooling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the controller is mounted on the front surface of the board using traditional mounting methods, then the board layout is simple and easy to manufacture, but the height restrictions are violated and heat dissipation is poor
Solution Approach 1:
The controller is mounted on the rear surface of the board instead of the conventional front surface. This inversion of the mounting location allows the board to meet height restrictions while maintaining manufacturing feasibility through the lane reversal mechanism
Solution Approach 2:
The controller mounting is moved from the front surface dimension to the rear surface dimension of the board. This dimensional change in mounting location resolves the height constraint issue while the lane reversal technique addresses the signal routing challenges
2Temperature
If the controller is mounted on the rear surface of the board, then heat dissipation is improved and height restrictions are met, but the signal line crossings increase and board layout complexity increases
Solution Approach 1:
The lane order is reversed for the rear surface mounting configuration. By inverting the lane sequence (e.g., lane 0 connects to physical lane 7, lane 1 to physical lane 6, etc.), the signal routing complexity is reduced despite the rear surface mounting position
Solution Approach 2:
The lane ordering parameter is changed based on the mounting surface. Different lane mapping configurations are used for front surface versus rear surface mounting, optimizing the signal routing for each scenario and reducing overall system complexity
3Adaptability or versatility
If the lane order is changed to accommodate rear surface mounting, then the board layout flexibility is improved, but the signal integrity may be compromised due to trace rearrangement
Solution Approach 1:
The physical layer interface circuit is designed to support multiple lane ordering configurations (standard order and reversed order). This multi-functionality allows the same hardware to adapt to different mounting surfaces while maintaining signal integrity through appropriate configuration selection
Solution Approach 2:
The lane mapping is made dynamic and configurable based on the mounting surface detection. The system can automatically or manually select the appropriate lane ordering (standard or reversed) to maintain optimal signal integrity for the specific physical configuration
Data Source
AI summary
A controller includes a physical layer interface circuit configured to support a first port and a second port both conforming to a PCIe standard, the first port including a first number of lanes with a first order, the second port including a second number of lanes with a second order, and the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via traces arranged in an order in which at least a part of the first order and at least a part of the second order are changed based on Lane Reversal conforming to the PCIe standard.