PCIe Clock Detection Circuit for Stable L1.2 to L0 Wake-Up
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Solution Overview
Problem
PCIe devices experience card dropouts when transitioning from the L1.2 low power state back to the L0 active state, leading to system instability and user experience issues.
Innovation Solution
A PCIe clock detection circuit comprising a clock detector, a clock receiver, a counter, a multiplexer, and an AND gate, which detects the amplitude of a clock signal, generates a reference clock signal, and ensures proper synchronization of the Phase-Locked Loop (PLL) to prevent incorrect frequency locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PCIe device transitions from L1.2 low power state to L0 active state, then power saving is improved, but system stability deteriorates due to card dropouts
Solution Approach 1:
The patent applies preliminary action by detecting the clock signal amplitude and generating a detection output signal before the PCIe device fully transitions from L1.2 to L0 state. This early detection mechanism prepares the system in advance, ensuring the PLL is properly synchronized before full operation resumes, thereby preventing card dropouts while maintaining power saving benefits
Solution Approach 2:
The patent implements feedback by continuously monitoring the clock signal amplitude through the clock detector and using the detection output signal to control the PLL operation. This feedback loop ensures that the system only proceeds with the state transition when clock signal stability is confirmed, thereby maintaining system reliability during power state transitions
2Device complexity
If the clock signal amplitude is not properly detected, then device complexity is reduced, but manufacturing precision deteriorates due to incorrect frequency locking
Solution Approach 1:
The patent applies segmentation by dividing the clock detection function into distinct modular components: a clock detector for amplitude detection, a signal generator for creating detection output, and a controller for managing the PLL based on detection results. This modular segmentation maintains manufacturing precision while making the overall system more manageable and less complex
Solution Approach 2:
The patent introduces an intermediary detection mechanism between the clock signal source and the PLL. The clock detector acts as an intermediary that conditions and validates the clock signal before it reaches the PLL, ensuring accurate frequency locking without requiring complex direct coupling between components
3Productivity
If the PLL starts operating before clock signal stabilizes, then productivity is improved, but reliability deteriorates due to card dropouts
Solution Approach 1:
The patent applies preliminary action by implementing a detection phase before the PLL fully operates. The clock detector prepares and validates the clock signal amplitude in advance, generating a detection output signal that authorizes PLL operation only when conditions are met, thus ensuring reliability without significantly delaying productivity
Solution Approach 2:
The patent implements dynamics by making the PLL operation conditional and adaptive based on real-time clock signal detection. The system dynamically adjusts the PLL activation timing based on clock signal stability, allowing fast transitions when conditions are favorable while preventing card dropouts when conditions are not met, thus balancing productivity and reliability
Data Source
AI summary
A PCIe clock detection circuit includes a clock detector, a clock receiver, a counter coupled to the clock receiver, a multiplexer coupled to the counter, and an AND gate coupled to the clock detector and the multiplexer. The clock detector is used to detect amplitude of a clock signal and generate a clock detection signal accordingly. The clock receiver is used to generate a reference clock signal according to the clock signal. The counter is used to generate a counter signal according to the reference clock signal. The multiplexer is used to generate a MUX output signal according to the counter signal and a reference signal. The AND gate is used to generate a clock detection output signal according to the clock detection signal and the MUX output signal.