PCI Express Link Segmentation for Bandwidth and Power Optimization
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Solution Overview
Problem
The existing PCI Express architecture inefficiently utilizes bandwidth and power as all traffic between components travels on the same link, regardless of data packet priority, leading to suboptimal resource allocation.
Innovation Solution
The solution involves configuring multiple PCI Express links with a combination of unidirectional and differentially driven transmitter and receiver signal pairs, allowing for separate links to handle different types of traffic and data packets, optimizing bandwidth and power usage by assigning appropriate link widths and data rates based on traffic patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all traffic between PCI Express components travels on the same link, then the link structure is simple and easy to implement, but bandwidth utilization is inefficient and power consumption is high
Solution Approach 1:
The patent segments a single wide PCI Express link into multiple separate links, each handling specific traffic types. For example, a x16 link is divided into multiple x4 or x8 links, allowing different traffic priorities to be routed through different segments, thereby improving bandwidth utilization efficiency while maintaining manageable complexity
Solution Approach 2:
The patent applies local quality by assigning different characteristics to different links based on traffic requirements. High-priority traffic is routed through links with higher data rates or lower latency, while low-priority traffic uses other links, optimizing resource allocation for each local segment
2Device complexity
If all traffic between PCI Express components travels on the same link, then the link configuration is simple, but power consumption is high due to continuous operation at high data rates
Solution Approach 1:
The patent introduces dynamic power management by enabling independent power state transitions for each link. Links can transition to lower power states (L1, L2, L3) based on traffic demands, allowing the system to reduce power consumption during low-activity periods while maintaining responsiveness for high-priority traffic
Solution Approach 2:
By segmenting traffic across multiple links, the patent enables selective power management where only active links consume high power. Idle links can be placed in low-power states, significantly reducing overall power consumption while maintaining the capability to quickly activate links when needed
3Productivity
If multiple links are created to segregate traffic, then bandwidth utilization improves and power efficiency increases, but the system complexity increases
Solution Approach 1:
The patent implements universal link management capabilities that can handle multiple traffic types across multiple links. The PCI Express switch and root complex are designed with multi-functional support for link aggregation, routing, and management, allowing the same infrastructure to efficiently manage both single-link and multi-link configurations
Solution Approach 2:
The patent merges multiple separate links into a unified logical interface for higher-level protocols and software. While physically separate, the links are managed as a cohesive unit through link aggregation and unified routing tables, reducing the perceived complexity for applications while maintaining the performance benefits of physical separation
4Use of energy by stationary object
If multiple links are created to segregate traffic, then power consumption reduces through selective low-power states, but the device complexity increases
Solution Approach 1:
The patent employs dynamic power management with automatic link state transitions based on real-time traffic monitoring. The system dynamically adjusts link power states without requiring complex manual configuration, using standardized PCI Express power management protocols to achieve power savings while maintaining simple operation
Solution Approach 2:
The patent implements self-service power management where the PCI Express hardware automatically monitors traffic patterns and adjusts link power states without external intervention. The system autonomously transitions links to low-power states when idle and activates them when traffic is detected, reducing the need for complex external power management infrastructure
Data Source
AI summary
A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of K lanes and each lane of the set of N lanes consisting of a unidirectional and differentially driven transmitter signal pair and a unidirectional and differentially driven receiver signal pair, wherein K and N are independently whole positive integers equal to or greater than 1.