PCIe Link Reconfiguration via M-PHY for Power Reduction
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Solution Overview
Problem
Conventional load/store communication protocols, such as PCIe™, are not power-efficient and have complex link management schemes that do not scale down well for mobile devices, leading to inefficiencies in power consumption and system performance.
Innovation Solution
A low-power interconnect technology that combines a conventional PCIe™ protocol stack with a low-power physical unit, such as M-PHY, to enable efficient power management and optimized link training, while maintaining performance by leveraging existing PCIe™ components and minimizing flexibility to suit fixed configurations in mobile devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PCIe protocol is used for communication between devices, then high communication speed is achieved, but power consumption increases
Solution Approach 1:
The patent implements dynamic link reconfiguration that allows the interconnect to adapt its operational parameters (such as link width and speed) based on current system needs. The link can be dynamically adjusted between different configurations including x16, x8, x4, and x1 modes, enabling the system to optimize power consumption by using narrower links when full bandwidth is not required, while maintaining high-speed capability when performance is needed.
2Adaptability or versatility
If PCIe link management scheme is implemented to support multiple form factors, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the link management functionality into distinct components: capability structures that advertise supported link configurations, and a reconfiguration mechanism that handles transitions between configurations. The capability structure is divided into specific fields (DLRC capability, DLRC control, DLRC status) that separately manage different aspects of link reconfiguration, simplifying the overall management complexity while maintaining support for multiple form factors.
Solution Approach 2:
The patent uses parameter changes in capability structures to enable adaptability across different form factors. The DLRC capability field contains bits that indicate supported link reconfiguration options, and the system dynamically adjusts link parameters (width, speed) based on these capability advertisements and system requirements, allowing the same hardware to adapt to various form factor requirements without increasing fundamental complexity.
3Productivity
If link reconfiguration is performed during runtime, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-service reconfiguration mechanism where the system automatically manages link reconfiguration based on capability advertisements and runtime requirements. The DLRC control and status registers enable the system to autonomously negotiate and execute link reconfiguration without requiring complex external management, improving productivity by allowing dynamic adaptation while keeping the reconfiguration mechanism relatively simple through standardized capability reporting.
Data Source
AI summary
In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.