PCIe Chip Power-On Sequencing for 20 ms Reset Timing
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Solution Overview
Problem
The power-on process of Peripheral Component Interconnect Express (PCIE) chips takes too long, failing to meet the 20 millisecond timing requirement of the PCIE protocol, leading to potential failures.
Innovation Solution
The method involves starting the processor of the PCIE chip when its first clock signal stabilizes, receiving a reset signal from the host after its second clock signal stabilizes, and executing the power-on operation before the second clock signal stabilizes, thereby reducing the duration of the power-on process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor is started after the second clock signal stabilizes, then the system stability is improved, but the power-on duration exceeds the 20 millisecond requirement
Solution Approach 1:
The processor is started in advance based on the stabilization of the first clock signal before the second clock signal stabilizes. This preliminary action allows the processor to be ready before the host sends the reset signal, thereby reducing the power-on duration while maintaining system stability through proper sequencing of operations.
Solution Approach 2:
The clock signal stabilization process is segmented into two independent phases: the first clock signal stabilization that triggers processor startup, and the second clock signal stabilization that triggers the reset signal. This segmentation allows overlapping execution of processor initialization and clock stabilization, reducing total power-on time.
2Duration of action of moving object
If the processor is started early based on the first clock signal, then the power-on duration is reduced, but the timing coordination with the host becomes more complex
Solution Approach 1:
Two distinct clock signals serve as intermediaries to decouple the processor startup timing from the host reset signal timing. The first clock signal acts as an intermediary to trigger processor startup independently, while the second clock signal acts as an intermediary to trigger the reset signal, simplifying the overall timing coordination despite the early startup.
Data Source
AI summary
A power-on operation execution method and apparatus are provided. The method includes: starting a processor of the chip in response to the chip being connected to a host and a frequency of a first clock signal of the chip being switched to a stable state; receiving a reset signal transmitted from the host, the reset signal being transmitted in response to a frequency of a second clock signal of the host being switched to a stable state; and executing a power-on operation in response to the reset signal, a time point at which the frequency of the first clock signal is switched to the stable state being earlier than a time point at which the frequency of the second clock signal is switched to the stable state.