Phase Change Memory Cell Structure for Lower Programming Current
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Solution Overview
Problem
In phase change memory (PCM) devices, the contact area between the phase change layer and electrodes is typically large, leading to high programming currents and slow switching times, which are limitations in memory device performance.
Innovation Solution
The contact area between the phase change layer and electrodes is reduced by adjusting the thickness of the phase change layer, allowing for smaller contact areas and enabling lower programming currents and faster switching times through the use of a memory device structure where the phase change layer is disposed between the sidewalls of electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the contact area between phase change layer and electrodes is reduced, then programming current is lowered and switching speed is improved, but manufacturing precision requirements increase due to lithography critical dimension limitations
Solution Approach 1:
The patent transitions from controlling contact area in the lateral plane (x-y dimensions) to controlling it in the vertical dimension (z-axis) by adjusting phase change layer thickness. This dimensional shift allows contact area reduction without being constrained by lithography critical dimensions, thereby lowering programming current while maintaining manufacturability
Solution Approach 2:
The patent changes the critical parameter from lateral contact dimensions (constrained by lithography) to vertical layer thickness (controllable by deposition/etching processes). By modifying the thickness parameter of the phase change layer, the contact area is reduced, achieving lower programming current and faster switching without exceeding lithography capabilities
2Loss of time
If the contact area between phase change layer and electrodes is reduced, then switching time is decreased, but device complexity increases due to precise fabrication requirements
Solution Approach 1:
The patent changes the controlling parameter from lateral dimensions to vertical thickness, which can be precisely controlled through standard deposition and etching processes. This parameter transformation reduces switching time while avoiding the need for complex lithography modifications
Solution Approach 2:
The patent applies local quality control by precisely controlling the thickness of the phase change layer in the vertical dimension, allowing different regions to have optimized contact areas. This localized control achieves fast switching without requiring complex overall device structure modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in lower programming currents and faster switching times, enhancing the performance of the memory device by reducing the contact area between the phase change layer and electrodes.
Implementation Method 1
after the current passes through the bottom electrode, the bottom electrode generates thermal energy
Implementation Method 2
the state of a function area in the phase change material is switched between crystalline and amorphous
Data Source
AI summary
A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.