Phase Change Memory Diode Self-Alignment via Dummy Gate Lattice

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Solution Overview

Problem

Conventional phase change memory devices face challenges in achieving high integration due to diode contact hole formation issues, such as shape deformation and side robe phenomena, which lead to electrical defects, especially when using dipole type apertures for forming contact holes with small pitches and diameters.

Innovation Solution

The proposed solution involves forming a highly integrated phase change memory device with a semiconductor substrate having parallel conductive stripe patterns and dummy gate electrodes, which allows for self-alignment of diode contact holes, reducing the need for small-pitch apertures and preventing shape deformation by creating a lattice structure with interlayer dielectric patterns and dummy gate electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If dipole type aperture is used to form contact holes with small pitch and diameter for high integration, then integration density is improved, but shape deformation and side robe phenomena occur leading to electrical defects

Engineering Contradiction:
Improveintegration densityVSAvoidcontact hole shape precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The aperture is divided into multiple segments (quadrupole type with four distinct openings) instead of using a single dipole aperture. This segmentation allows each opening to be optimized for specific contact hole formation, reducing shape deformation and side robe effects while maintaining small pitch and diameter for high integration density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The quadrupole aperture introduces asymmetric opening configurations that are optimized for different contact hole positions and orientations. This asymmetric design compensates for the side robe phenomena and shape deformation that occur with symmetric dipole apertures, enabling precise contact hole formation at small pitches.

Inventive Principle:
Principle #4Asymmetry

2Quantity of substance

If contact holes are formed with small diameter to increase diode density, then integration is improved, but shape deformation occurs during formation

Engineering Contradiction:
Improvediode densityVSAvoidcontact hole shape
Core Design Contradiction:
Quantity of substanceVSShape

Solution Approach 1:

The quadrupole aperture is designed and positioned in advance to account for and compensate for expected shape deformation during contact hole formation. The aperture geometry is pre-calibrated to produce correctly shaped contact holes even at small diameters, preventing deformation before it occurs rather than correcting it afterward.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If small pitch aperture arrangement is used to form maximum number of contact holes, then integration density is improved, but side robe phenomena increase causing electrical defects

Engineering Contradiction:
Improvecontact hole quantityVSAvoidside robe phenomena
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The quadrupole aperture design converts the potentially harmful side robe effects into beneficial patterns by strategically positioning four openings that work together to cancel out or redirect side robe energy away from adjacent contact holes. This transforms what would be a harmful interference pattern into a configuration that actually protects contact hole integrity.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS8580636B2Highly integrated phase change memory device having micro-sized diodes and method for manufacturing the same
Publication Date: 2013.11.12 SK HYNIX INC
  • US8580636B2 patent drawing
  • US8580636B2 patent drawing
  • US8580636B2 patent drawing

AI summary

A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extending in parallel to each other in a first direction to form a striped pattern. A gate electrode is formed in the peripheral area and dummy gate electrodes are formed in the cell area and extending in a second direction perpendicular to the first direction of the impurity regions. An interlayer dielectric layer pattern exposes portions of the cell area and the peripheral area and a PN diode is formed in a space defined by a pair of dummy gate electrodes and a pair of interlayer dielectric layer patterns.