PCM Sidewall Liner Structure for Resistance Drift Suppression
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Solution Overview
Problem
Phase change memory (PCM) devices suffer from resistance drift, particularly in the high-resistance state (HRS), affecting computing accuracy and reliability in computation-in-memory (CIM) applications, with issues such as large cell sizes, narrow memory windows, and high write power requirements.
Innovation Solution
The implementation of sidewall liners on phase change material portions, combined with a bottom liner, to control resistance and stabilize resistance states, incorporating nitrogen or carbon atoms into the sidewall liner material to enhance resistivity and reduce power consumption, thereby suppressing resistance drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCM devices are used for memory-based computing applications, then scalability and non-volatility are improved, but resistance drift occurs particularly in the high-resistance state affecting computing accuracy
Solution Approach 1:
A sidewall liner material is introduced as an intermediary between the phase change material and the surrounding environment. This sidewall liner has a resistivity between 10^-3 and 10^0 ohm-cm, which is higher than the crystalline phase of the PCM but lower than the amorphous phase. This intermediary layer suppresses resistance drift by providing a stable resistance reference and preventing unwanted electrical interactions, thereby improving computing accuracy while maintaining the PCM's scalability and non-volatility
2Area of stationary object
If conventional PCM structures are used, then device simplicity is maintained, but cell sizes are large and memory windows are narrow
Solution Approach 1:
The PCM device structure is segmented by introducing a sidewall liner that divides the device into distinct functional regions: a core phase change material region and a surrounding sidewall liner region. This segmentation allows independent optimization of each region's properties, enabling smaller cell sizes while maintaining adequate memory windows through controlled electrical characteristics in each segment
3Power
If conventional PCM structures are used, then manufacturing simplicity is maintained, but write power requirements are high
Solution Approach 1:
The electrical parameters of the device are changed by introducing the sidewall liner with specific resistivity characteristics (10^-3 to 10^0 ohm-cm). This parameter change modifies the overall resistance profile of the PCM device, enabling more efficient current distribution and reducing the power required for write operations while maintaining compatibility with existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances PCM performance and reliability by stabilizing resistance values, reducing power consumption, and enabling smaller cell sizes for improved accuracy and efficiency in CIM applications.
Implementation Method 1
The sidewall liner material comprises a material having an electrical conductivity between 10^-3 and 10^0 ohm-cm, which is higher than an electrical conductivity of a crystalline phase of the phase change material and lower than an electrical conductivity of an amorphous phase of the phase change material
Data Source
AI summary
A device structure may be provided by forming a bottom electrode and a heater element within a dielectric material layer; depositing and patterning a continuous layer stack including a bottom liner layer, a phase change material layer including a phase change material, and a top electrode material layer; and forming at least one sidewall liner by depositing and patterning a sidewall liner material. At least one sidewall liner is formed on at least one sidewall of a patterned portion of the continuous layer stack.The at least one sidewall liner includes a material having an electrical conductivity that is higher than an electrical conductivity of an amorphous phase of the phase change material.