Phase Change Memory Symmetric Access for Voltage Drop Reduction
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Solution Overview
Problem
Parallel writing in phase change memory devices results in high voltage drops on wordlines due to high write currents, limiting the ability to write multiple data simultaneously, leading to unacceptable dissipation and preventing the parallel writing of more than one datum.
Innovation Solution
The method involves reversing the order of accessing memory cells to minimize current flowing in selected wordlines by selecting cells symmetrically arranged with respect to the middle point of the wordline, reducing the voltage drop and allowing simultaneous writing of multiple data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel writing is performed in phase change memory devices, then multiple data can be written simultaneously, but high voltage drops on wordlines occur due to high write currents
Solution Approach 1:
The patent applies inversion by reversing the conventional sequential access order to a symmetric random access pattern. Instead of accessing memory cells in sequential order (0, 1, 2, 3...), the method accesses cells in symmetric pairs from both ends toward the center (0 and 7, then 1 and 6, then 2 and 5, then 3 and 4). This inverted approach balances the current distribution across the wordline, causing current to flow in opposite directions that partially cancel each other's voltage drop effects, thereby enabling parallel writing while maintaining acceptable voltage levels.
2Speed
If high write currents are used for parallel writing, then writing speed increases, but power dissipation becomes unacceptable
Solution Approach 1:
The patent applies the counterweight principle by using symmetric random access to create opposing current flows that act as electrical counterweights. When writing to symmetric cell pairs, current flows through the wordline in opposite directions, creating voltage drops of equal magnitude but opposite polarity. These opposing effects cancel each other out, allowing the system to maintain lower net voltage drops and reduce power dissipation while still achieving parallel writing of multiple data at high speed.
Data Source
AI summary
A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.