Phase Change Memory Device Vertical PN Diode Junction Area
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Solution Overview
Problem
Conventional phase change memory devices with vertical PN diodes face challenges in increasing the junction area between N-type and P-type areas, leading to reduced operating currents and hindered integration due to the small junction area.
Innovation Solution
The phase change memory device features a semiconductor substrate with N-type silicon pillars and P-type silicon patterns formed on the sidewalls, creating a larger junction area between the N-type and P-type areas, enhancing the operating current and integration by sharing a common N-type pillar between two adjoining cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of N-type epi-silicon is increased to increase junction area, then the junction area between N-type and P-type areas increases, but the degree of integration is adversely influenced
Solution Approach 1:
The patent transitions from a planar junction structure to a three-dimensional vertical junction structure by forming P-type silicon patterns on the sidewalls of N-type silicon pillars. This vertical configuration increases the junction area by utilizing the pillar's surface area in addition to the top surface, effectively adding a dimensional aspect to the junction formation without increasing the lateral footprint of the device.
Solution Approach 2:
The patent implements a nested structure where P-type silicon patterns are formed on the sidewalls of N-type silicon pillars, creating a concentric arrangement. The P-type regions are essentially nested around the N-type pillar, maximizing the junction interface area within a compact vertical space, thereby increasing junction area without proportionally increasing the overall device area.
2Device complexity
If conventional vertical PN diodes are used, then the device structure is simple, but the junction area becomes too small leading to decreased operating currents
Solution Approach 1:
The patent enhances the conventional vertical PN diode by adding sidewall P-type patterns around the N-type pillar, transforming the junction from a simple planar interface to a multi-faceted three-dimensional structure. This increases the junction area and consequently the operating current while maintaining the vertical diode architecture and relative structural simplicity.
Solution Approach 2:
The patent applies local quality modification by forming P-type silicon patterns specifically on the sidewalls of the N-type pillars rather than uniformly throughout. This localized doping approach concentrates the junction formation at critical interfaces, increasing the effective junction area and operating current in specific regions while maintaining overall device simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the junction area and operating current, improving the operation characteristics and enabling higher integration density compared to conventional designs.
Implementation Method 1
Phase change memory devices work on the basis of the fact that a phase change occurs in a phase change layer interposed between a bottom electrode and a top electrode. One particular phase change of interest comprises a reversible transition between an ordered crystalline phase state and that of an amorphous phase state. This reversible phase transition can be induced by flowing electrical current between the bottom electrode and the top electrode.
Implementation Method 2
In order to form the vertical PN diodes, in conventional arts, after growing epi-silicon doped with N-type impurities, the P-type impurities are then ion-implanted into the upper end of the grown N-type epi-silicon.
Data Source
AI summary
A phase change memory device includes a semiconductor substrate active region, a plurality of first conductivity type silicon pillars, and a plurality of second conductivity type silicon patterns. The plurality of first conductivity type silicon pillars is formed on the semiconductor active region such that each first conductivity type silicon pillar is provided for two adjoining cells. The plurality of second conductivity type silicon patterns is formed on the plurality of first conductivity type silicon pillars such that two second conductivity type silicon patterns are formed on opposite sidewalls of each first conductivity type silicon pillars. Two adjoining cells together share only one first conductivity type silicon pillar and each adjoining cell is connected to only one second conductivity type silicon pattern which constitutes a PN diode which serves as a single switching element for each corresponding cell.