Phase Change Memory Diode With Bulging PN Junction
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Solution Overview
Problem
Phase change memory devices face challenges in achieving high integration due to deteriorating current drivability and reliability as diode areas decrease, and increasing diode size leads to bridge phenomena between adjoining diodes.
Innovation Solution
A phase change memory device with a diode having a contact hole with a critical dimension greater at the middle portion than the upper and lower portions, featuring a triple-layered insulation structure and a vertical PN diode with a silicon epi-layer, where the second insulation layer has a higher etch rate, allowing for increased diode area without expanding the upper surface, thus enhancing current drivability and preventing bridge phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of diodes is increased to improve current drivability, then the current drivability is improved, but the bridge phenomenon occurs between adjoining diodes
Solution Approach 1:
The contact hole is designed with non-uniform cross-sectional area, being larger at the middle portion and smaller at the upper and lower portions. This local variation in geometry allows the diode area to be increased at the middle portion for improved current drivability while keeping the upper surface area limited to prevent bridge phenomena between adjoining diodes.
2Area of stationary object
If the CD of contact holes for diodes is increased to increase diode area, then the diode area is increased, but the bridge phenomenon is likely to occur between adjoining diodes
Solution Approach 1:
The critical dimension of the contact hole is varied locally along its depth, with the middle portion having a larger CD than the upper and lower portions. This allows the diode area to be increased without proportionally increasing the upper surface CD, thereby preventing bridge phenomena while still achieving larger diode area for improved current drivability.
3Quantity of substance
If the surface area of DRAM electrodes is increased to achieve high charge storing capacity, then the charge storing capacity is improved, but the integration level is reduced
Solution Approach 1:
Instead of increasing the surface area of electrodes in the planar direction, the invention increases the charge storing capacity by extending the electrode structure in the vertical dimension. The contact hole structure with larger middle portion provides additional volume for charge storage while maintaining a compact footprint, thereby improving integration level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves current drivability and reliability of phase change memory devices by increasing the diode area selectively at the middle portion, preventing bridge phenomena and maintaining high integration levels.
Implementation Method 1
a method for manufacturing the same comprises the steps of forming an insulation layer on a semiconductor substrate, the insulation layer being defined with a contact hole which has a CD that is greater at a middle portion thereof than an upper portion and a lower portion thereof
Implementation Method 2
Phase change memory devices function by having a phase change occurs in a phase change layer interposed between a bottom electrode and a top electrode. This phase change layer transitions between an ordered crystalline state to an unordered amorphous crystalline state. This phase change transition can be driven by an electric current flowing between the bottom electrode and the top electrode.
Implementation Method 3
This phase change transition can be driven by an electric current flowing between the bottom electrode and the top electrode
Data Source
AI summary
A phase change memory device that has a diode with an enlarged, i.e., bulging, PN interfacial junction and a corresponding fabrication method are presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a diode, and a phase change memory cell. The insulation layer is placed on the semiconductor substrate and has a contact hole which is wider in a middle portion than the lower and upper portions of the contact hole. The diode is formed within the contact hole and PN interfacial junction at the wider middle portion of the diode within the contact hole. The phase change memory cell is formed on top of the diode.