Phase-Change Memory Saturation Pulse Drift Control

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Solution Overview

Problem

Resistance drift in multiple-level phase-change memory devices remains a challenging issue, especially in partially amorphous intermediate states, affecting the reliability of read operations.

Innovation Solution

Applying a saturation pulse of heating current to the memory cell following a writing operation to stabilize the resistance and minimize further drift, with the pulse being less than 1 μs after programming, thereby accelerating and controlling resistance drift for predictable read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a saturation pulse is applied to accelerate resistance drift saturation, then resistance stability is improved, but device complexity increases due to additional circuit operations

Engineering Contradiction:
Improveresistance stabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A saturation pulse is applied immediately after programming to preemptively drive resistance drift to saturation, ensuring stability before the read operation. This preliminary action eliminates the need for complex compensation circuits during reading, as the resistance is already stabilized by the saturation pulse.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a saturation pulse is applied following programming, then resistance drift is minimized, but operation time increases

Engineering Contradiction:
Improveresistance drift controlVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The saturation pulse is applied periodically at specific intervals after programming (e.g., within 1 μs to 1 ms), creating a structured temporal sequence that efficiently saturates resistance drift without requiring continuous monitoring or extended operation times.

Inventive Principle:
Principle #19Periodic action

3Ease of operation

If resistance drift is allowed to occur naturally, then device operation is simpler, but read accuracy deteriorates due to unpredictable resistance changes

Engineering Contradiction:
Improveoperation simplicityVSAvoidread accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The saturation pulse temporarily changes the resistance parameter by driving it to saturation, which then stabilizes the resistance value. This parameter transformation converts unpredictable resistance drift into a stable, predictable state that can be accurately read without complex compensation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively stabilizes the resistance of memory cells, reducing resistance drift and ensuring reliable read operations by accelerating the drift process, allowing for accurate state determination during subsequent reads.

Implementation Method 1

Applying a saturation pulse of heating current to the memory cell following a writing operation to stabilize the resistance and minimize further drift

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

multiple-level phase-change memory devices... resistance-changeable material... initially programmed to a first state... drift to a second state

Methodology Applied
Scientific EffectPhase change: Phase Change

Data Source

PatentUS7778079B2Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices
Publication Date: 2010.08.17 SAMSUNG ELECTRONICS CO LTD
  • US7778079B2 patent drawing
  • US7778079B2 patent drawing
  • US7778079B2 patent drawing

AI summary

In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.