Phase Change Memory Side Wall Chalcogenide Layer
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Solution Overview
Problem
In phase change memory devices using chalcogenide layers, the resistance values vary with increased rewriting cycles, leading to a higher electric current requirement, which compromises the number of rewriting operations and durability due to an enlarged phase change region.
Innovation Solution
A semiconductor device design where the chalcogenide layer is formed as a side wall within a contact hole, with a buried insulation film and electrodes, ensuring the layer is entirely used as a phase change region, maintaining a constant volume and reducing the electric current required for rewriting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chalcogenide layer is formed in conventional structures (on lower heater electrode with upper electrode), then the basic memory cell structure is achieved, but the phase change region volume increases with rewriting cycles causing resistance value variation and increased energy consumption
Solution Approach 1:
The chalcogenide layer is repositioned from a planar structure on the heater electrode to a vertical side wall structure within a contact hole. This dimensional change confines the phase change region to a precise volume defined by the contact hole geometry, preventing volume expansion during rewriting cycles and maintaining constant resistance values.
Solution Approach 2:
The chalcogenide layer is positioned only in the side wall region of the contact hole, creating a localized phase change region with controlled volume. This local placement ensures that only the necessary minimal volume undergoes phase changes, preventing the enlargement problem that occurs in conventional extended layer structures.
2Productivity
If the number of rewriting operations is increased, then more data can be stored and accessed, but the resistance values vary and electric current requirement increases
Solution Approach 1:
The vertical side wall configuration within the contact hole provides precise three-dimensional confinement of the chalcogenide layer. This geometric constraint maintains a constant phase change region volume throughout rewriting operations, ensuring stable resistance values and enabling high rewriting durability without performance degradation.
3Use of energy by moving object
If the chalcogenide layer volume is reduced to minimize energy consumption, then less energy is required for phase change, but the layer may not be entirely used as phase change region in early rewriting stages
Solution Approach 1:
The side wall configuration within the contact hole creates a well-defined three-dimensional phase change region where the entire chalcogenide layer volume is effectively utilized from the first rewriting operation. The vertical geometry ensures complete and uniform phase change throughout the layer, maximizing energy efficiency while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for stable rewriting operations at a constant current level, preventing the phase change region from increasing in volume with repeated cycles, thus ensuring reliable and efficient memory cell performance.
Implementation Method 1
In the reset operation, the chalcogenide layer is supplied with sufficient Joule heat to be melted and then rapidly cooled to create an amorphous state exhibiting a high resistance
Implementation Method 2
The chalcogenide layer is varied in crystal structure depending upon a heating temperature and a cooling time and exhibits a high resistance value in an amorphous state and a low resistance value in a crystalline state
Data Source
AI summary
In a semiconductor device, a phase change layer is formed as a side wall and is therefore reduced in volume. Even if the number of times of rewriting is small, the phase change layer is entirely used as a phase change region. Therefore, the phase change region is not increased in volume even if the number of times of rewriting is increased. Since the volume of the phase change region is not changed, an electric current level required for rewriting is constant. Thus, the semiconductor device having a memory cell capable of carrying out stable rewriting is obtained.