PCRAM Memory Cell Structure With Thermal Preservation Layer

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Solution Overview

Problem

Flash memory faces scaling difficulties, prompting the exploration of alternative nonvolatile memory technologies, with phase change memory (PCM) being a promising option due to its fast read and write times, non-destructive reads, and high scalability.

Innovation Solution

The integration of a memory cell structure within an integrated circuit, comprising a substrate, interconnect structure, passivation layers, conductive pads, and transistors, where a memory cell includes a bottom electrode, thermal preservation layer, variable resistance layer, and top electrode, with the thermal preservation layer enhancing heat confinement and reducing reset current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If flash memory is scaled down to increase storage density, then storage capacity is improved, but manufacturing precision and reliability deteriorate due to scaling difficulties

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturing precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent changes the fundamental operating parameters from flash memory's charge storage mechanism to PCM's phase state mechanism. By utilizing the distinct electrical resistance differences between crystalline and amorphous phases of changeable material, the system achieves high storage density without being constrained by traditional flash memory scaling limitations, thereby maintaining manufacturing precision while increasing storage capacity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent directly applies phase transitions of changeable material as the core storage mechanism. The material transitions between crystalline (low resistance) and amorphous (high resistance) phases through controlled heating, enabling reliable data storage. This phase transition mechanism is inherently scalable and does not suffer from the same manufacturing precision degradation as continued flash memory scaling.

Inventive Principle:
Principle #36Phase transitions

2Speed

If phase change memory is implemented to achieve fast read/write times and high scalability, then speed and adaptability are improved, but device complexity increases due to additional structural components

Engineering Contradiction:
Improveread and write timesVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the heating function and thermal confinement into a single integrated electrode structure. The bottom electrode serves dual purposes: applying heat for phase transitions and confining thermal energy through its thermal preservation layer. This consolidation reduces device complexity compared to separate heating and thermal management components, while maintaining fast read/write speeds through efficient thermal control.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a thermal preservation layer as an intermediary between the bottom electrode and the changeable material. This layer mediates thermal energy transfer, improving heating efficiency and confining heat to the active region. The intermediary enables faster phase transitions (improving speed) while the layer's thin-film nature minimizes additional device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If thermal preservation layer is added to enhance heat confinement, then energy efficiency is improved, but device complexity and manufacturing precision requirements increase

Engineering Contradiction:
Improvereset currentVSAvoidmanufacturing precision
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a spatial gradient in thermal properties through the thermal preservation layer. The layer is positioned specifically at the bottom electrode interface where heat confinement is most needed, with its thickness and material properties optimized for localized thermal management. This targeted approach improves reset current efficiency while limiting manufacturing precision requirements to only the critical thermal preservation layer region.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite material structures in the bottom electrode assembly, combining conductive materials with thermal preservation materials having different thermal conductivities. This composite structure enables simultaneous electrical conduction and thermal confinement functions. The composite design improves energy efficiency through better thermal management while the modular nature of composite material deposition simplifies manufacturing compared to monolithic structures.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the performance of phase change random access memory (PCRAM) by ensuring effective thermal confinement, lowering reset current, and enhancing memory cell performance, addressing scaling challenges in flash memory.

Implementation Method 1

the thermal preservation layer enhancing heat confinement and reducing reset current

Methodology Applied
Scientific EffectThermal confinement: Thermal Insulation

Implementation Method 2

a phase of a PCM is employed to represent a unit of data

Methodology Applied
Scientific EffectPhase change: Phase Change

Data Source

PatentUS20240016072A1Memory cell, integrated circuit, and manufacturing method of memory cell
Publication Date: 2024.01.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240016072A1 patent drawing
  • US20240016072A1 patent drawing
  • US20240016072A1 patent drawing

AI summary

A memory cell includes a bottom electrode, a thermal preservation layer, a first dielectric layer, a variable resistance layer, and a top electrode. The bottom electrode includes a first electrode and a second electrode spatially separated from the first electrode. The thermal preservation layer is partially sandwiched between the first electrode and the second electrode. The first dielectric layer laterally surrounds the bottom electrode and the thermal preservation layer. The variable resistance layer is disposed on the second electrode, the thermal preservation layer, and the first dielectric layer. The top electrode is disposed on the variable resistance layer.