PCRAM Write Control via Segmented Set and Reset Pulses
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Solution Overview
Problem
Current phase change random access memory (PCRAM) apparatuses face challenges in optimizing write operation speed and data reliability due to simultaneous set and reset operations requiring large electric currents and differing programming times, leading to inefficient use of programming periods and potential data state deterioration.
Innovation Solution
A phase change random access memory apparatus that allows independent programming of set and reset data at different times using separate write pulses, enabling independent control of set and reset operations and reducing current consumption by optimizing pulse profiles and using a comparing unit to prevent redundant data writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If set and reset operations are performed simultaneously in PCRAM, then write operation speed is improved, but programming time is unnecessarily extended due to the set operation requiring longer programming time
Solution Approach 1:
The patent segments the write operation into separate set operations and reset operations that can be independently controlled and executed at different times. Instead of simultaneously writing both set and reset data, the controller separates these operations so that reset data can be written independently without waiting for the longer set operation to complete, thereby optimizing the overall programming time while maintaining write operation speed
Solution Approach 2:
The patent applies preliminary action by performing reset operations before set operations when both types of data need to be written. Since reset operations require less programming time, executing them first allows the system to complete shorter operations ahead of time, avoiding the bottleneck created by waiting for longer set operations to complete before initiating reset operations
2Productivity
If large electric current is applied to program PCRAM cells, then programming capability is improved, but current consumption increases and programming time for set data becomes excessively long
Solution Approach 1:
The patent applies partial action by using different current levels optimized for each operation type: higher current for reset operations that require less time, and lower current for set operations that require more time. This prevents excessive current consumption while maintaining adequate programming capability for both operation types, avoiding the need to continuously apply high current that would increase energy consumption
3Speed
If set and reset data are simultaneously written to memory cells, then write operation is accelerated, but the state of cell data deteriorates due to interference between operations
Solution Approach 1:
The patent segments simultaneous write operations into separate set and reset operations executed at different time intervals. This temporal separation eliminates interference between the two operations, preventing data state deterioration while still maintaining efficient write performance through independent optimization of each operation type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes programming time, enhances data reliability, and optimizes the use of programming periods, improving the overall efficiency and speed of write operations while reducing current consumption and preventing unintended data storage.
Implementation Method 1
the phase change material in each cell is changed to a low resistance state to represent a set data whereas it is changed to a high resistance state to represent a reset data
Implementation Method 2
Writing reset data to the phase change random access memory apparatus requires a large amount of electric current to be applied for a short time
Data Source
AI summary
The disclosed phase change random access memory apparatus is configured to program a predetermined phase change memory cell in the phase change memory apparatus in response to a plurality of write instructions applied at independent points of time.