PCSL Asynchronous Logic for Sub-Threshold Voltage Scaling
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Solution Overview
Problem
Current digital circuits operating in the sub-threshold voltage regime face challenges with operational robustness due to process, voltage, and temperature variations, leading to unpredictable performance and inefficiencies, especially in synchronous-logic designs, which are not adequately robust or energy-efficient for ultra-low power applications.
Innovation Solution
The implementation of a novel asynchronous-logic realization approach using Static-Logic with a Pre-Charged Static-Logic (PCSL) circuit design, integrating a Request sub-circuit and buffers into a dual-rail QDI circuit, which is more robust and efficient in accommodating PVT variations, achieving smaller IC area, higher speed, and lower power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous-logic design is used for sub-threshold operation, then circuit operation can be synchronized, but operational robustness deteriorates due to PVT variations
Solution Approach 1:
The patent replaces synchronous-logic design (which relies on global clock synchronization) with asynchronous-logic design that uses local handshake protocols and self-timing mechanisms. This substitution eliminates the mechanical constraint of global clock distribution and enables robust operation in sub-threshold regime where PVT variations make synchronous timing unpredictable.
Solution Approach 2:
The patent changes the operating parameters by designing circuits to operate in the sub-threshold voltage regime (below transistor threshold voltage) and uses adaptive body biasing to dynamically adjust transistor characteristics. This parameter change enables ultra-low power operation while maintaining operational robustness against PVT variations through the intrinsic properties of asynchronous logic.
2Use of energy by moving object
If sub-threshold voltage operation is used, then power dissipation is reduced to ultra-low levels, but speed deteriorates significantly
Solution Approach 1:
The patent implements dynamic voltage scaling capability that allows the circuit to adaptively adjust its operating voltage based on performance requirements. The circuit can operate at ultra-low sub-threshold voltages for maximum energy efficiency when speed demands are modest, and can be 'dialled-up' to higher voltages when speed demands increase, providing a flexible power/speed trade-off.
Solution Approach 2:
The patent employs periodic pre-charging of logic nodes in the asynchronous circuit design, where nodes are periodically charged to full voltage levels during idle periods and then allowed to discharge during computation. This periodic action enables the circuit to maintain signal integrity and operate reliably at sub-threshold voltages while achieving ultra-low power dissipation.
3Area of stationary object
If transistor geometry is reduced for scaling, then device density is increased, but PVT variations worsen and become increasingly variable
Solution Approach 1:
The patent implements self-calibration techniques where the asynchronous circuit automatically adjusts its operation to compensate for PVT variations. The handshake protocols and completion detection circuits inherently adapt to varying propagation delays caused by process variations, eliminating the need for external calibration or trimming and providing robust operation despite scaled transistor geometry.
Solution Approach 2:
The patent designs the asynchronous logic with inherent timing margins and uses adaptive body biasing that anticipates and compensates for PVT variations before they affect circuit operation. The body biasing circuits pre-adjust transistor characteristics to counteract expected variations, providing a cushion against the increased variability inherent in scaled geometries.
Data Source
AI summary
Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.