Peaking Inductor Embedded in T-Coil for Compact Chip Space
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Solution Overview
Problem
Existing semiconductor device fabrication techniques inefficiently use chip space due to separate and laterally-spread arrangements of on-chip peaking inductors and T-coils, leading to suboptimal space utilization and quality factor tradeoffs.
Innovation Solution
A back-end-of-line interconnect structure with stacked metallization levels, where a T-coil and a peaking inductor are arranged in overlapping configurations, allowing for a compact composite structure that efficiently uses available space by integrating the inductors within the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate and laterally-spread arrangements are used for on-chip peaking inductor and T-coil, then individual placement and routing is simplified, but chip space utilization becomes inefficient
Solution Approach 1:
The patent merges the previously separate on-chip peaking inductor and T-coil into a single integrated structure. The peaking inductor is formed within the same lateral footprint as the T-coil by utilizing intermediate metallization levels, thereby combining two previously separate components into one unified device that improves space utilization while maintaining manufacturing simplicity
Solution Approach 2:
The patent transitions from a two-dimensional lateral arrangement to a three-dimensional stacked arrangement by placing the peaking inductor coil in an intermediate metallization level between the T-coil's metallization levels. This vertical integration allows both components to occupy the same lateral space while remaining electrically distinct, effectively utilizing the third dimension to resolve the space utilization issue
2Reliability
If completely separate lateral areas are used for T-coil and on-chip peaking inductor, then individual keep out zones can be optimized, but overall space efficiency deteriorates
Solution Approach 1:
The patent implements a nested configuration where the peaking inductor is embedded within the lateral boundaries of the T-coil structure. The peaking inductor coil in the intermediate metallization level is positioned such that its projection overlaps with the T-coil's lateral footprint, allowing both components to share the same lateral space while maintaining their respective keep out zones for reliability
3Loss of energy
If on-chip inductor size is increased to improve quality factor, then energy loss to substrate decreases, but chip area occupancy increases
Solution Approach 1:
The patent resolves the quality factor versus area tradeoff by moving the inductor construction into the third dimension. By forming the peaking inductor coil in an intermediate metallization level between the substrate and the T-coil, the design achieves low substrate loss without increasing the lateral footprint, as the vertical stacking allows multiple inductive elements to occupy the same planar area
Data Source
AI summary
Structures that include a peaking inductor and a T-coil, and methods associated with forming such structures. A back-end-of-line interconnect structure includes a first metallization level, a second metallization level, and a third metallization level arranged between the first metallization level and the second metallization level. The T-coil includes a first inductor with a first coil arranged in the first metallization level and a second inductor with a second coil arranged in the second metallization level. A peaking inductor includes a coil arranged in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end-of-line interconnect structure with an overlapping arrangement.