Conductive Plating Enhancement Layer for Semiconductor Damascene
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Solution Overview
Problem
As semiconductor devices approach critical dimensions smaller than 45 nm, conventional copper seed layers often result in non-uniform plating and voids due to pinching off damascene openings, leading to increased resistance and the need for modified plating tools, and alternative seed layers like ruthenium increase resistance further.
Innovation Solution
A conductive and optically transparent plating enhancement layer, such as tin oxide or indium oxide, is used to facilitate uniform copper plating by reducing the overall resistance and allowing thicker deposition without affecting pattern recognition, serving as both a conductivity enhancer and etch hard mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a copper seed layer is deposited by PVD process, then the seed layer can be formed, but it results in non-conformal deposition and pinches off damascene openings at critical dimensions less than 45 nm
Solution Approach 1:
The patent introduces an intermediary layer (mandrel layer or planarization layer) between the substrate and the copper seed layer. This intermediary layer prevents the seed layer from directly contacting and pinching off the damascene openings, while still allowing conformal deposition and subsequent copper plating to proceed uniformly.
Solution Approach 2:
The patent segments the seed layer formation process by separating it from direct contact with the damascene openings through the intermediary layer. This segmentation allows the seed layer to be deposited conformally without being constrained by the opening geometry, thus avoiding pinching off while maintaining coverage.
2Object-generated harmful factors
If the copper seed layer is thinned or alternative seed layers such as ruthenium are utilized, then pinching off is avoided, but the resistance of the metal stack increases
Solution Approach 1:
The intermediary layer acts as a mediator that allows a sufficiently thick copper seed layer to be deposited without pinching off the damascene openings. This enables the use of thicker seed layers with lower resistance while preventing the harmful pinching off effect through the physical separation provided by the intermediary layer.
3Manufacturing precision
If plating tool modifications are made for uniform plating, then plating uniformity can be improved, but the cost and complexity increase
Solution Approach 1:
The patent applies preliminary action by depositing the intermediary layer before the copper seed layer and damascene patterning. This pre-established structure ensures that subsequent copper plating proceeds uniformly across the wafer without requiring modifications to the plating tool, as the intermediary layer has already created the necessary conditions for uniform deposition.
4Device complexity
If conventional seed layers are used, then the process is simple, but voids and non-uniform plating occur at critical dimensions smaller than 45 nm
Solution Approach 1:
The intermediary layer serves as a mediator that enables conventional simple PVD deposition processes to achieve uniform plating at critical dimensions below 45 nm. By introducing this intermediate structure, the process remains relatively simple while the intermediary layer ensures that the copper seed layer deposits conformally without pinching off openings or creating voids.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a transparent conductive oxide plating enhancement layer ensures uniform copper plating across the wafer, reducing resistance and voltage drop, thereby improving plating uniformity and reducing the need for costly tool modifications, while maintaining optical transparency and pattern integrity.
Implementation Method 1
The use of conductive oxides for different applications has been proposed... a conductive and optically transparent plating enhancement layer, such as tin oxide or indium oxide, is used to facilitate uniform copper plating by reducing the overall resistance
Implementation Method 2
The copper seed layer is typically deposited by a physical vapor deposition (PVD) process or a variant thereof such as an ionized PVD (IPVD) process
Implementation Method 3
Electrochemical deposition of copper has been found to provide the most cost-effective manner in which to deposit a copper metallization layer
Data Source
AI summary
Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.