Pentacene OFET n-type interlayer for low voltage operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Pentacene organic field-effect transistors (OFETs) using polymer films as charge trapping dielectrics face issues with high operation voltage, low programming/erasing speed, poor endurance, and retention degradation due to positively charged defects at the pentacene/polymer interface, which impede hole transfer and result in high working voltages.
Innovation Solution
Incorporating an n-type semiconductor buffer layer or interlayer between the polymer charge-trapping dielectric and pentacene, which reduces the height of the hole-barrier by electrostatic induction, thereby decreasing programming/erasing gate voltages and improving the endurance and retention characteristics of pentacene OFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polymer films are used as charge trapping dielectric in pentacene OFETs, then charge storage capability is improved, but operation voltage becomes high and programming/erasing speed becomes slow
Solution Approach 1:
An n-type semiconductor interlayer is introduced as an intermediary between the polymer charge trapping dielectric and the pentacene layer. This interlayer mediates the interaction between the two materials, reducing the hole-barrier height at the interface through electrostatic induction from trapped charges, thereby lowering the operation voltage required for device operation while maintaining the charge storage capability of the polymer dielectric.
Solution Approach 2:
The introduction of the n-type semiconductor interlayer changes the electrical parameters at the dielectric-semiconductor interface. Specifically, it modifies the hole-barrier height and charge transfer characteristics, enabling more efficient charge trapping and reducing the voltage required for programming and erasing operations.
2Reliability
If polymer films are used as charge trapping dielectric in pentacene OFETs, then charge storage capability is improved, but programming/erasing speed becomes slow
Solution Approach 1:
The n-type semiconductor interlayer acts as a mediator that facilitates faster charge transfer between the polymer dielectric and the pentacene channel. By reducing the hole-barrier height, it enables more rapid charge trapping during programming and charge release during erasing, thereby improving programming/erasing speed while preserving charge storage capability.
Solution Approach 2:
The interlayer modifies the charge transfer kinetics at the interface by changing the energy barrier parameters. This results in faster charge trapping and release processes, improving the speed of programming and erasing operations without compromising the amount of charge that can be stored.
3Reliability
If positively charged defects exist at pentacene/polymer interface, then charge trapping is enhanced, but hole transfer is impeded and working voltage increases
Solution Approach 1:
The n-type semiconductor interlayer serves as a mediator that decouples the charge trapping function from the charge transfer function. It allows positive charges to be trapped at the polymer interface while simultaneously providing a pathway for hole transport through the interlayer to the pentacene channel, thereby maintaining charge trapping effectiveness while reducing the voltage penalty associated with interface defects.
Solution Approach 2:
The interlayer changes the electrical parameters at the interface by introducing n-type carriers that compensate for the positively charged defects. This modification reduces the effective hole-barrier height and lowers the working voltage required for device operation while preserving the charge trapping capability provided by the polymer dielectric.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of an n-type semiconductor buffer or interlayer effectively reduces the height of the hole-barrier at the interface, leading to lower programming/erasing voltages, enhanced field-effect mobility, and improved endurance and retention characteristics of pentacene OFETs, making them more suitable for practical applications.
Implementation Method 1
Incorporating an n-type semiconductor buffer layer or interlayer between the polymer charge-trapping dielectric and pentacene, which reduces the height of the hole-barrier by electrostatic induction
Data Source
AI summary
A method for enhancing the performance of pentacene organic field-effect transistor (OFET) using n-type semiconductor interlayer: an n-type semiconductor thin film was set between the insulating layer and the polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type semiconductor layer is 1˜200 nm. The induced electrons at the interface of n-type semiconductor and polymer electret lead to the reduction of the height of the hole-barrier formed at the interface of polymer and pentacene, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET, adjusting the height of hole barrier at the interface of polymer and pentacene to a reasonable scope by controlling the quantity of induced electrons in n-type semiconductor layer, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics.