Asynchronous Per-Core DCVS for Multicore CPU Power Management
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Solution Overview
Problem
Current methods for managing power in multicore CPUs of portable computing devices are inadequate, as they do not effectively control power consumption and thermal management independently across multiple cores, leading to inefficiencies and potential overheating.
Innovation Solution
Implementing dynamic clock and voltage scaling (DCVS) algorithms that run independently on each core of a multicore CPU, allowing for asynchronous and independent control of clock frequencies and voltages based on idle time or workload, enabling each core to set its own frequency and voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single centralized power controller manages all cores in a multicore CPU, then the control structure is simple and unified, but power management efficiency and thermal control are inadequate for individual cores
Solution Approach 1:
The patent divides the centralized power controller into multiple independent per-core power controllers, each managing power for a specific core. This segmentation allows independent optimization of power and frequency for each core based on its specific workload and thermal conditions, resolving the contradiction between simple control structure and efficient power management.
Solution Approach 2:
Each per-core power controller implements local power management policies tailored to individual core characteristics and workload demands. This enables differentiated frequency scaling and voltage control for each core, improving overall power management efficiency while maintaining manageable complexity through modular design.
2Stability of the object's composition
If clock frequencies are synchronized across all cores, then the system maintains uniform operation, but power consumption cannot be optimized for individual core workloads
Solution Approach 1:
The patent implements dynamic frequency scaling for each core independently through per-core power controllers. Each controller adjusts its core's clock frequency in real-time based on workload demands, allowing cores with light workloads to reduce frequency and save power while cores with heavy workloads maintain higher frequencies for performance.
Solution Approach 2:
Instead of uniformly scaling frequencies across all cores, the system applies frequency scaling selectively to individual cores based on their specific needs. This partial action approach reduces power consumption by lowering frequencies only where and when necessary, rather than applying uniform scaling to the entire multicore system.
3Ease of operation
If power management policies are applied uniformly across all cores, then implementation is straightforward, but thermal hotspots cannot be addressed locally
Solution Approach 1:
The patent segments the power management system into independent per-core controllers that can implement thermal management policies locally. Each controller monitors its own core's thermal conditions and adjusts power/frequency accordingly, enabling local hotspot mitigation while maintaining relatively simple implementation through modular architecture.
Data Source
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AI summary
A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.