Per-Lane Duty Cycle Correction for Memory DQ Timing
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Solution Overview
Problem
Existing semiconductor memory devices have fixed, non-configurable circuitry for generating phase controlled internal clock signals, which limits their ability to adjust timing characteristics in response to channel effects like noise and crosstalk, affecting the operation of external devices.
Innovation Solution
Incorporating configurable timing circuitry, such as a phase splitter and selective capacitive loading circuitry, at each DQ pin to adjust the duty cycle of the phase controlled internal clock signal, allowing for real-time tuning of timing characteristics to match external device operations while reducing power and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed, non-configurable circuitry is used to generate phase controlled internal clock signals, then device complexity is reduced, but adaptability to different timing requirements deteriorates
Solution Approach 1:
The patent implements dynamic duty cycle correction by making the clock signal generation circuitry configurable after manufacture. The system transitions from fixed circuitry to dynamically adjustable circuitry that can modify timing characteristics in response to channel effects and external device requirements, resolving the contradiction between simplicity and adaptability.
Solution Approach 2:
The patent changes the timing parameters (duty cycle, phase) of the internal clock signal from fixed values to configurable parameters. By allowing these parameters to be adjusted based on operating conditions and external device requirements, the system achieves adaptability without significantly increasing overall device complexity.
2Adaptability or versatility
If configurable timing circuitry is added to adjust duty cycle, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent segments the duty cycle correction functionality into lane-specific configurations rather than requiring global reconfiguration. Each DQ pin can have independent timing adjustments, which distributes the complexity across multiple simple, identical modules rather than one complex centralized unit, thereby improving adaptability with minimal complexity increase.
3Reliability
If duty cycle is adjusted to correct timing characteristics, then signal integrity improves, but power consumption increases
Solution Approach 1:
The patent adjusts timing parameters (duty cycle, phase) to optimize signal integrity for each lane based on measured channel effects. By making targeted, minimal adjustments only where needed rather than globally changing all timing parameters, the system improves signal integrity while minimizing the additional power consumption required for adjustment.
Data Source
AI summary
The present disclosure relates generally to improved systems and methods for control of one or more timing signals in a memory device. More specifically, the present disclosure relates to configurable duty cycle correction at one or more DQ pins (e.g., data input/output (I/O) pins) of the memory device. For example, the memory device may include a configurable phase splitter and/or selective capacitive loading circuitry implemented to adjust the duty cycle of a timing signal at one or more DQ pins during and/or after manufacture of the memory device. Accordingly, the memory device may include increased flexibility and granularity of control over the one or more timing signals.