Periodic Idle-Event Testing of SoC Functional Units
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Solution Overview
Problem
Existing techniques for identifying degraded System on Chip (SoC) functional components are insufficient, particularly in applications where frequent cold boot events are not feasible, leading to undetected faults and potential performance degradation or failure, such as in data centers and automotive systems.
Innovation Solution
Implementing periodic in-field self-testing of SoC functional units using scan patterns generated from updated fault models, applied during idle events to detect faults without shutting down the SoC, and utilizing per-IP isolation to save power and resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If periodic in-field self-testing is implemented using scan patterns, then fault detection accuracy is improved, but system downtime and power consumption increase
Solution Approach 1:
The patent implements periodic in-field self-testing of SoC functional units by applying scan patterns at scheduled intervals during idle events. This periodic approach ensures faults are detected regularly without requiring continuous testing, thus maintaining fault detection accuracy while minimizing system downtime and power consumption.
Solution Approach 2:
The patent prepares scan patterns and test configurations in advance during system initialization or idle periods. By pre-loading test data and configuring test environments before actual testing is needed, the system can execute tests quickly during idle events without causing significant downtime or requiring complex real-time setup procedures.
2Reliability
If scan patterns are applied during idle events, then fault detection is achieved without shutting down the SoC, but testing frequency is limited by idle event availability
Solution Approach 1:
The patent enables the SoC to perform self-testing during its own idle events without requiring external testing equipment or system shutdown. The functional units test themselves autonomously by applying scan patterns and evaluating results, which maintains system availability while utilizing otherwise wasted idle time for testing purposes.
Solution Approach 2:
The patent designs the testing mechanism to serve multiple functions: it detects faults in functional units, utilizes idle time effectively, consumes minimal power, and maintains system availability. The scan pattern application infrastructure is integrated into the normal operational framework, allowing the same hardware resources to serve both operational and testing functions.
3Use of energy by moving object
If per-IP isolation is used during testing, then power consumption and resource usage are reduced, but system complexity increases
Solution Approach 1:
The patent applies per-IP (per-intellectual property) isolation during testing, where each functional unit or IP block is independently isolated and tested. This segmentation allows testing to be confined to specific regions of the SoC, reducing power consumption and resource usage by keeping only the necessary test infrastructure active while maintaining manageable complexity through modular isolation strategies.
Data Source
AI summary
Periodic in-field testing of system on chip functional units is described. In accordance with the described techniques, a scan pattern associated with a fault is applied to a functional unit during an idle event of the functional unit, the scan pattern defining a sequence of input signals. An output of the functional unit is received in response to the scan pattern. A status of the functional unit with respect to the fault is output based on the output of the functional unit and an expected output for the scan pattern.