PET Detector Clock Synchronization Using Phase-Tuned Reset Signals

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Solution Overview

Problem

Conventional clock synchronization methods for PET detectors result in unsynchronized time counters due to differences in transmission and detection environments, leading to inaccuracies in medical imaging.

Innovation Solution

A system and method for clock synchronization involving a reset signal generator that generates preliminary reset signals with different phases, receives feedback data from detectors, determines an optimum phase, and transmits a reset signal for synchronized time counter starting or resetting across multiple detectors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single reset signal is transmitted to multiple PET detectors, then the system structure is simple, but detection synchronization is poor due to transmission and detection environment differences

Engineering Contradiction:
Improvesignal transmission systemVSAvoiddetection synchronization
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the single reset signal into multiple preliminary reset signals with different phases. Each detector receives a customized reset signal phase that compensates for its specific transmission and detection environment differences, thereby achieving precise synchronization without requiring complex centralized control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by allowing each detector to have its own optimal reset signal phase. The system determines the best phase for each detector based on its individual characteristics, enabling each component to operate at its optimal synchronization point rather than forcing a uniform signal across all detectors.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If different phase reset signals are transmitted to each detector, then detection synchronization is improved, but device complexity increases

Engineering Contradiction:
Improvedetection synchronizationVSAvoidsignal transmission system
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by determining the optimal phase for each detector in advance through a phase determination process. This preliminary calibration allows the system to use simple phase selection during actual operation, avoiding the need for complex real-time adjustment mechanisms while maintaining high synchronization precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the phase parameter of reset signals to adapt to different detector characteristics. By varying only the phase parameter rather than the entire signal structure, the system achieves precise synchronization with minimal increase in device complexity, as the underlying transmission infrastructure remains unchanged.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If conventional reset signal method is used, then the system is easy to operate, but time counter synchronization is poor leading to image inaccuracies

Engineering Contradiction:
Improvesystem operationVSAvoidimage accuracy
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent implements self-service by enabling detectors to automatically determine their own optimal phase through feedback from received preliminary reset signals. This self-calibration mechanism eliminates the need for manual synchronization adjustment, maintaining ease of operation while achieving precise time counter synchronization for accurate medical imaging.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12458316B2Systems and methods for clock synchronization
Publication Date: 2025.11.04 SHANGHAI UNITED IMAGING HEALTHCARE
  • US12458316B2 patent drawing
  • US12458316B2 patent drawing
  • US12458316B2 patent drawing

AI summary

The present disclosure relates to a device and methods for clock synchronization. The device may include a first synchronization component and one or more second synchronization components. The first synchronization component may be configured to transmit a first synchronization signal to the one or more second synchronization components. Each second synchronization component of the one or more second synchronization components may be configured to generate a second synchronization signal based on the first synchronization signal and transmit the second synchronization signal to one or more detectors. The second synchronization signal may be configured to reset a clock of a detector of the one or more detectors corresponding to the each second synchronization component.