Phase Frequency Detector Missing-Edge Control for PLL Gain Reversal
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Solution Overview
Problem
Conventional Phase Frequency Detectors (PFDs) face limitations due to nonzero reset delay, leading to gain reversal and slowed PLL frequency acquisition, potentially causing failure in acquiring frequency lock.
Innovation Solution
Implementing control circuitry that detects missing edges of reference and feedback clocks, generating blocking signals to block the next rising edges of the opposite clock, effectively increasing the positive gain of the Phase Frequency Detector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PFD with nonzero reset delay is used, then the PFD can guarantee minimum pulse width, but the linear range is reduced to less than 4π and gain reversal occurs
Solution Approach 1:
The patent applies preliminary action by detecting missing clock edges before they cause gain reversal. The control circuitry identifies when a clock edge is missing and proactively blocks subsequent rising edges of the opposite clock, preventing the gain reversal condition from occurring in the first place. This advance intervention maintains measurement precision while preserving the minimum pulse width guarantee.
Solution Approach 2:
The patent introduces an intermediary control circuitry between the conventional PFD and the charge pump. This intermediary detects missing edges and generates blocking signals that prevent gain reversal, acting as a mediator that resolves the conflict between maintaining minimum pulse width and preserving linear detection range. The control circuitry translates the output signals from the PFD into appropriate blocking actions.
2Reliability
If nonzero reset delay is implemented, then dead-zone issue is avoided, but PLL frequency acquisition speed is dramatically slowed
Solution Approach 1:
The patent applies skipping by allowing the PFD to operate with nonzero reset delay while using control circuitry to detect and skip over problematic conditions. When a missing edge is detected, the system rushes through the acquisition process by blocking subsequent edges and forcing immediate correction, thereby maintaining dead-zone avoidance while dramatically speeding up frequency acquisition.
Solution Approach 2:
The patent changes the operational parameters of the PFD by dynamically blocking clock edges based on detected conditions. The control circuitry modifies the effective reset delay behavior by selectively blocking rising edges, transforming the fixed nonzero delay into a variable parameter that can be adjusted to maintain both reliability and speed.
3Device complexity
If conventional PFD operation is used, then circuit complexity is kept simple, but positive gain is reduced and frequency lock acquisition may fail
Solution Approach 1:
The patent applies universality by designing control circuitry that performs multiple functions: it detects missing edges, generates blocking signals, and controls the charge pump. This multi-functional approach increases reliability for frequency lock acquisition while adding only moderate complexity, as the same control logic handles multiple critical tasks rather than requiring separate dedicated circuits for each function.
Data Source
AI summary
Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.