Memory Wake-Up Protocol Using PFET Bitline Precharge
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Solution Overview
Problem
Existing memory devices face issues with steep power supply droop and noise during wake-up from sleep modes due to current surges, which can lead to active memory failures and data loss, and previous solutions involve high overhead, additional logic, or slow charging methods that are impractical.
Innovation Solution
A multi-stage wake-up protocol using PFETs to gradually charge bitcells and bitlines, with a predetermined delay between wake signals, minimizing additional logic and leveraging existing PFETs to reduce core voltage supply droop and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory instances are switched from deep-sleep mode to functional mode, then the memory instances become operational, but a large current surge occurs on the power supply causing voltage droop
Solution Approach 1:
The patent applies preliminary action by pre-charging bitlines before activating memory instances from deep-sleep mode. The bitlines are charged to a first voltage level before the memory instances are fully activated, and then charged to a second voltage level after activation. This staged charging approach prepares the bitlines in advance, reducing the sudden current surge when memory instances are activated and preventing voltage droop on the power supply.
2Device complexity
If a single wake signal is used to activate all memory instances, then the wake-up process is simple, but large current surges cause power supply droop and noise
Solution Approach 1:
The patent applies segmentation by dividing the wake-up process into multiple stages with different wake signals. A first wake signal activates memory instances and initiates bitline charging to a first voltage level. A second wake signal subsequently charges bitlines to a second voltage level. This segmented approach reduces the current surge by distributing the activation process over time, preventing power supply droop and noise while maintaining manageable control logic complexity.
3Power
If bitlines are charged sequentially one at a time, then power supply droop is minimized, but the wake-up process becomes extremely slow with high circuit overhead
Solution Approach 1:
The patent applies dynamics by using dynamic voltage levels for bitline charging based on memory instance activation state. After memory instances are activated by the first wake signal, bitlines are charged to a first voltage level. Subsequently, bitlines are charged to a second voltage level. This dynamic charging approach minimizes power supply droop by charging bitlines in stages rather than all at once, while avoiding the extreme slowness of sequential individual charging. The process achieves a balance between power stability and wake-up speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protocol effectively reduces power supply droop and noise during wake-up, preventing data loss and improving the reliability of memory devices without requiring excessive additional logic or circuitry.
Implementation Method 1
The charging of these instances 8 from sleep mode to functional mode can cause a current surge on the power supply... the bitline precharge PFETs charge the bitline pairs to a first voltage level... the plurality of bitline precharge PFETs charges the bitline pairs to a second voltage level
Data Source
AI summary
A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells.