PFET SiGe Channel With High-K Metal Gate
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Solution Overview
Problem
In advanced submicron FET devices, it is challenging to independently optimize the device parameters for PFET and NFET devices, as changes in one type of device can adversely affect the other, particularly in terms of threshold voltage control and carrier mobility, especially when using high-k gate dielectrics and metal gates.
Innovation Solution
The method involves depositing a SiGe layer using blanket epitaxial growth, followed by a first sequence of layers with a high-k dielectric and metal for PFET devices, and then removing these layers from NFET devices to re-form them with a second sequence of layers optimized for NFET devices, allowing independent optimization of device parameters by avoiding SiGe in the NFET channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SiGe layer is deposited using blanket epitaxial growth for PFET devices, then carrier mobility is improved, but device complexity increases due to selective removal and re-formation processes
Solution Approach 1:
The fabrication process is segmented into distinct phases: blanket deposition of SiGe layer, selective removal from NFET regions, and separate gate stack formation for PFET and NFET devices. This allows independent optimization of each device type while managing overall process complexity through systematic division of steps.
Solution Approach 2:
The SiGe layer is selectively extracted (removed) from NFET device regions using targeted etching processes, while being retained in PFET regions. This extraction enables different channel compositions for different device types from a single blanket deposition, resolving the contradiction between improved carrier mobility in PFET and avoidance of SiGe in NFET.
2Measurement precision
If high-k dielectric and metal gate layers are deposited for PFET devices, then threshold voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric constant (k-value) is changed by selecting high-k dielectric materials instead of traditional silicon dioxide. This parameter change enables better threshold voltage control and electrical performance in scaled devices, while the systematic fabrication process manages the increased manufacturing precision requirements through standardized deposition and etching sequences.
3Reliability
If device parameters are independently optimized for PFET and NFET, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process merges common steps (blanket SiGe deposition, high-k dielectric deposition, metal gate deposition) with selective steps (patterned removal, selective re-formation) to achieve independent optimization of PFET and NFET parameters. This combination approach enables performance optimization while consolidating where possible the fabrication steps.
Solution Approach 2:
The SiGe layer is deposited in advance (blanket epitaxial growth) before selective removal, and high-k dielectric/metal gates are deposited in preliminary sequences that can be selectively retained or removed. These preliminary actions establish a foundation that enables subsequent selective processing for independent device optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of threshold voltages and carrier mobility for both PFET and NFET devices, improving performance by allowing separate optimization of device parameters, which is critical for maintaining performance in deeply submicron devices with decreasing operating voltages.
Implementation Method 1
depositing onto a Si surface a SiGe layer using blanket epitaxial growth
Data Source
AI summary
In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.