Phase Change Memory Grain Size Segmentation
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Solution Overview
Problem
Phase change memories require high initial reset currents due to the HCP phase change materials' low resistivities, leading to increased power consumption and variability in reset currents across memory cells, necessitating more efficient methods for reducing initial reset currents and minimizing differences between initial and subsequent reset currents.
Innovation Solution
A phase change memory device is constructed with a fine-grain crystalline phase change layer and a coarse-grain crystalline phase change layer, where the fine-grain layer has a smaller average grain size and higher resistivity, and the coarse-grain layer has a larger average grain size, allowing for reduced initial reset currents and minimized differences between initial and subsequent reset currents by adjusting grain sizes and deposition conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If HCP phase change materials are used due to process variations requiring about 400°C fabrication temperature, then the memory device can be manufactured, but the initial reset current becomes very high leading to increased power consumption
Solution Approach 1:
The phase change layer is divided into two distinct layers: a first phase change layer with smaller grain size (5-15 nm) and a second phase change layer with larger grain size (15-30 nm). This segmentation allows each layer to contribute differently to the overall resistance, enabling the fine-grain first layer to provide high resistance that reduces the initial reset current requirement while maintaining manufacturability at 400°C
Solution Approach 2:
Different regions of the phase change element are given different grain sizes to optimize local properties. The first phase change layer near the heater has finer grains for higher resistance, while the second layer has coarser grains. This local quality differentiation enables the structure to achieve both manufacturability and reduced power consumption
2Reliability
If high initial reset currents are used to reset all phase change memory cells, then reset reliability is improved, but power consumption is unnecessarily increased for non-initial reset operations
Solution Approach 1:
The invention changes the physical parameter of grain size within the phase change material to control resistance. By creating a bi-layer structure with grain sizes of 5-15 nm and 15-30 nm respectively, the overall resistance is optimized to reduce initial reset current while maintaining reset reliability across all memory cells
3Ease of manufacture
If process variations in heater formation are accepted, then manufacturing simplicity is maintained, but different phase change memory cells require different reset currents increasing variability
Solution Approach 1:
The bi-layer phase change structure compensates for heater variations by creating localized resistance optimization. The fine-grain first layer provides consistent high resistance characteristics that mask variations in heater performance, while the coarse-grain second layer provides thermal mass. This local quality approach maintains manufacturing simplicity while improving reset current uniformity across cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces the initial reset current and the difference between initial and subsequent reset currents, optimizing power consumption and operational efficiency in phase change memory devices.
Implementation Method 1
The first phase change layer has a first grain size; and a second phase change layer over the first phase change layer. The second phase change layer has a second average grain size different from the first average grain size.
Implementation Method 2
The chalcogenide semiconductors with phase change capability have a crystalline state and an amorphous state. The resistivity ratios of the phase change materials in the amorphous and crystalline states are typically greater than 1000
Implementation Method 3
Some phase change materials, such as Ge—Sb—Te alloys, may have three possible structures, amorphous structure, face-centered cubic (FCC) structure, and hexagonal close packed (HCP) structure. Amorphous phase has high resistivities, HCP phase has low resistivities
Data Source
AI summary
A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.