Clock Duty Cycle Calibration Using Phase Clocks and Level Shifters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the decreasing operating voltages affect IC performance, particularly in level shifter circuits operating in different voltage domains, necessitating improved clock duty cycle adjustment and calibration to maintain optimal operation.
Innovation Solution
A clock duty cycle adjustment and calibration circuit comprising a ring oscillator, level shifters, a duty cycle adjustment circuit, and a duty cycle calibration circuit, which generates and adjusts clock signals across different voltage domains without relying on analog voltage measurement, using programmable reference generators and filters to achieve precise duty cycle calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog voltage measurement methods are used for duty cycle calibration, then calibration can be performed, but circuit complexity and area usage increase
Solution Approach 1:
The patent replaces analog voltage measurement methods with a digital counting-based calibration approach. The duty cycle calibration circuit uses phase clock signals and counters to measure duty cycles digitally, eliminating the need for complex analog voltage measurement circuits while achieving the same calibration precision.
Solution Approach 2:
The patent introduces phase clock signals as an intermediary to facilitate duty cycle measurement. Instead of directly measuring analog voltages, the system uses phase clock signals generated by a ring oscillator to create countable time intervals that represent duty cycle proportions, enabling precise digital measurement without analog complexity.
2Measurement precision
If duty cycle calibration circuit is designed to be independent of input signal duty cycles, then calibration accuracy improves, but circuit design complexity increases
Solution Approach 1:
The patent segments the duty cycle calibration process into multiple independent stages: generating phase clock signals, counting clock cycles during different duty cycle intervals, comparing counts to determine calibration status, and adjusting duty cycles accordingly. This segmentation allows each stage to be designed independently, improving overall calibration accuracy while managing design complexity through modular organization.
Solution Approach 2:
The patent implements a feedback mechanism where the duty cycle calibration circuit continuously monitors the actual duty cycle of output signals and adjusts them based on predetermined target values. The calibration process uses feedback from duty cycle measurements to iteratively improve accuracy, ensuring the circuit operates independently of input signal duty cycles while maintaining manageable design complexity through systematic control.
3Adaptability or versatility
If level shifters are used to operate circuits in different voltage domains, then voltage domain compatibility is achieved, but performance deteriorates due to decreasing operating voltages
Solution Approach 1:
The patent changes the operating voltage parameter of the level shifter circuit by providing different voltage domains (first voltage domain and second voltage domain) to different stages of the ring oscillator. This allows the circuit to adapt to different voltage requirements while maintaining proper oscillation and signal levels, thereby improving reliability in multi-voltage domain environments without sacrificing voltage domain compatibility.
Data Source
AI summary
A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to generate a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to adjust a second duty cycle of a first clock output signal responsive to a set of control signals or a phase difference between a first phase clock signal and a second phase clock signal of the first set of phase clock signals. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.