Phase Detection Circuit for Harmonic Lock-Free Clock Generation
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Solution Overview
Problem
Existing clock generation circuits in semiconductor devices face issues with harmonic lock when the internal clock signal is synchronized with the falling edge of the division clock signal, leading to degraded operation reliability and increased power consumption.
Innovation Solution
A phase detection circuit and clock generation circuit that includes a division circuit, clock selection circuit, phase detector group, and edge detector to generate and control clock signals, ensuring synchronization with the rising edge of the division clock signal, thereby preventing harmonic lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the internal clock signal is generated by performing delay-locked operation based on division clock signal, then the frequency division is achieved, but the phase may be synchronized with falling edge causing harmonic lock
Solution Approach 1:
The patent applies preliminary action by detecting the edge type (rising or falling) of the division clock signal before the delay-locked loop completes its locking process. The edge detector identifies whether the locked phase corresponds to a rising or falling edge, and based on this detection, the controller selectively inverts the phase of the division clock signal. This preliminary detection and conditional phase inversion prevents harmonic lock from occurring in the first place, rather than correcting it after occurrence.
2Measurement precision
If the phase detection circuit continuously monitors both rising and falling edges, then the phase detection accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent implements partial action by having the edge detector focus on detecting only the relevant edge type (either rising or falling edge) based on the locked phase condition, rather than continuously monitoring both edges with equal intensity. The controller selectively activates phase inversion only when needed to prevent harmonic lock, rather than continuously operating at full detection capacity. This reduces power consumption while maintaining sufficient phase detection accuracy for the specific operational requirements.
Data Source
AI summary
A clock generation circuit performs a delay-locked operation on a reference clock signal. The clock generation circuit is configured to perform the delay-locked operation by comparing the phases of a division reference clock signal and a feedback clock signal. After the delay-locked operation is completed, the clock generation circuit is configured to selectively invert the phase of the division reference clock signal by comparing the phases of the division reference clock signal and the delay feedback clock signal.