Accumulated Phase-to-Digital Conversion with Divide-by-N DPLL
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Solution Overview
Problem
Conventional digital phase-locked loops (DPLLs) face challenges with high power consumption and complex design due to the high-frequency operation of counter and time-to-digital converter components in accumulated phase-to-digital converters (APDCs), which require precise matching of signal path delays.
Innovation Solution
The proposed solution involves a novel APDC design using a divide-by-N module and a delta phase-to-digital converter, where the frequency of the target signal is divided by a divider ratio N, accumulating the divider ratio to generate an integer phase, and combining it with the digital phase difference to produce the accumulated phase, reducing power consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the counter and TDC operate at high frequencies to generate high-frequency output signals, then the DPLL can achieve high output frequency, but power consumption increases
Solution Approach 1:
The patent segments the accumulated phase measurement into two independent parts: integer cycles measured by a counter and fractional cycles measured by a TDC. By dividing the frequency of the output signal by the divider ratio N, the counter and TDC operate at lower frequencies (N times lower than the output signal frequency), reducing power consumption while still enabling high-frequency output generation through frequency multiplication in the phase accumulation process
Solution Approach 2:
The patent changes the operating frequency parameter of the counter and TDC by introducing a divider ratio N. The counter counts integer cycles at the divided frequency (output frequency / N), and the TDC measures fractional cycles at the same divided frequency. This parameter change allows the system to achieve high output frequency through phase accumulation mathematics rather than direct high-frequency operation of the measurement components
2Speed
If the counter and TDC operate at high frequencies, then high-frequency output signals can be generated, but design complexity increases due to precise signal path delay matching requirements
Solution Approach 1:
The patent segments the phase measurement function into separate integer counting (counter) and fractional measurement (TDC) paths. The counter accumulates integer cycles by dividing the output frequency by N, while the TDC independently measures fractional cycles at the same divided frequency. This segmentation eliminates the need for precise signal path delay matching between the two components, as they operate independently at lower frequencies and are combined through simple digital addition in the phase accumulation equation
Solution Approach 2:
The patent introduces a divider ratio N as an intermediary parameter that mediates between the high-frequency output signal and the lower-frequency counter/TDC operation. The divided frequency serves as a common reference frequency for both the counter and TDC, allowing them to operate at reduced frequencies without compromising the accuracy of the accumulated phase measurement, thereby simplifying the design requirements
Data Source
AI summary
Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by-N module that divides the frequency of the signal down by a divider ratio N. The divided signal is input to a delta phase-to-digital converter, which measures the phase difference between a rising edge of the divided signal and a rising edge of a reference signal. The accumulated divider ratios and the measured phase differences are combined to give an accumulated digital phase. Further techniques for varying the divider ratio N using a sigma-to-delta modulator are disclosed.